Patents Examined by Didarul Mazumder
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Patent number: 11830892Abstract: An image sensor with high quantum efficiency is provided. In some embodiments, a semiconductor substrate includes a non-porous semiconductor layer along a front side of the semiconductor substrate. A periodic structure is along a back side of the semiconductor substrate. A high absorption layer lines the periodic structure on the back side of the semiconductor substrate. The high absorption layer is a semiconductor material with an energy bandgap less than that of the non-porous semiconductor layer. A photodetector is in the semiconductor substrate and the high absorption layer. A method for manufacturing the image sensor is also provided.Type: GrantFiled: November 30, 2020Date of Patent: November 28, 2023Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chien-Chang Huang, Chien Nan Tu, Ming-Chi Wu, Yu-Lung Yeh, Ji Heng Jiang
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Patent number: 11823949Abstract: An embodiment is a device including a first fin extending from a substrate, a first gate stack over and along sidewalls of the first fin, a first gate spacer disposed along a sidewall of the first gate stack, and a first source/drain region in the first fin and adjacent the first gate spacer. The first source/drain region including a first insulator layer on the first fin, and a first epitaxial layer on the first insulator layer.Type: GrantFiled: May 10, 2021Date of Patent: November 21, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Tzu-Ching Lin, Tuoh Bin Ng
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Patent number: 11824030Abstract: An electronics package includes an electrically insulating substrate having a first surface and a second surface, an adhesive layer positioned on the first surface of the electrically insulating substrate, and an electrical component having a top surface coupled to the adhesive layer on a surface thereof opposite the electrically insulating substrate, the electrical component having contact pads on the top surface. Vias are formed through the electrically insulating substrate and the adhesive layer at locations corresponding to the contact pads by way of a mechanical punching operation, with each of the vias having a via wall extending from the second surface of the electrically insulating substrate to a respective contact pad. At each via, the electrically insulating substrate comprises a protrusion extending outwardly from the first surface thereof so as to cover at least part of the adhesive layer in forming part of the via wall.Type: GrantFiled: June 9, 2022Date of Patent: November 21, 2023Assignee: General Electric CompanyInventors: Christopher James Kapusta, Youichi Nishihara
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Patent number: 11824025Abstract: Semiconductor devices including electrically-isolated extensions and associated systems and methods are disclosed herein. An electrically-isolated extension may be coupled to a corresponding connection pad that is attached to a surface of a device. The electrically-isolated extensions may extend at least partially through one or more layers at or near the surface and toward a substrate or an inner portion thereof.Type: GrantFiled: August 20, 2021Date of Patent: November 21, 2023Assignee: Micron Technology, Inc.Inventors: Wei Zhou, Thiagarajan Raman
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Patent number: 11817413Abstract: A semiconductor package structure includes a conductive pad formed over a substrate. The structure also includes a passivation layer formed over the conductive pad. The structure also includes a first via structure formed through the passivation layer and in contact with the conductive pad. The structure also includes a first encapsulating material surrounding the first via structure. The structure also includes a redistribution layer structure formed over the first via structure. The first via structure has a lateral extending portion embedded in the first encapsulating material near a top surface of the first via structure.Type: GrantFiled: August 30, 2021Date of Patent: November 14, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Neng-Chieh Chang, Po-Hao Tsai, Ming-Da Cheng, Wen-Hsiung Lu, Hsu-Lun Liu
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Patent number: 11817409Abstract: A bonded structure can include a first reconstituted element comprising a first element and having a first side comprising a first bonding surface and a second side opposite the first side. The first reconstituted element can comprise a first protective material disposed about a first sidewall surface of the first element. The bonded structure can comprise a second reconstituted element comprising a second element and having a first side comprising a second bonding surface and a second side opposite the first side. The first reconstituted element can comprise a second protective material disposed about a second sidewall surface of the second element. The second bonding surface of the first side of the second reconstituted element can be directly bonded to the first bonding surface of the first side of the first reconstituted element without an intervening adhesive along a bonding interface.Type: GrantFiled: December 28, 2021Date of Patent: November 14, 2023Assignee: ADEIA SEMICONDUCTOR BONDING TECHNOLOGIES INC.Inventors: Belgacem Haba, Rajesh Katkar, Ilyas Mohammed, Javier A. DeLaCruz
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Patent number: 11817499Abstract: In certain embodiments, a semiconductor device includes a substrate having an n-doped well feature and an epitaxial silicon germanium fin formed over the n-doped well feature. The epitaxial silicon germanium fin has a lower part and an upper part. The lower part has a lower germanium content than the upper part. A channel is formed from the epitaxial silicon germanium fin. A gate is formed over the epitaxial silicon germanium fin. A doped source-drain is formed proximate the channel.Type: GrantFiled: June 29, 2022Date of Patent: November 14, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Shahaji B. More, Huai-Tei Yang, Shih-Chieh Chang, Shu Kuan, Cheng-Han Lee
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Patent number: 11805647Abstract: Embodiments of 3D memory devices and methods for forming the same are disclosed. In an example, a method for forming a 3D memory device is disclosed. A channel opening extending vertically is formed above a substrate. A semiconductor plug is formed in a lower portion of the channel opening. A memory film and a channel sacrificial layer are subsequently formed above the semiconductor plug and along a sidewall of the channel opening. A semiconductor plug protrusion protruding above the semiconductor plug and through a bottom of the memory film and the channel sacrificial layer is formed. A cap layer is formed in the channel opening and over the channel sacrificial layer. The cap layer covers the semiconductor plug protrusion. A semiconductor channel is formed between the memory film and the cap layer by replacing the channel sacrificial layer with a semiconductor material epitaxially grown from the semiconductor plug protrusion.Type: GrantFiled: February 3, 2021Date of Patent: October 31, 2023Assignee: YANGTZE MEMORY TECHNOLOGIES CO., LTD.Inventor: Hongbin Zhu
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Patent number: 11804450Abstract: A semiconductor device includes first and second members. In the first member, a first electronic circuit including a semiconductor element is formed. The second member is joined to an area of part of a first surface of the first member, and includes a second electronic circuit including a semiconductor element formed of a semiconductor material different from that of the semiconductor element of the first electronic circuit. An interlayer insulating film covers the second member and an area of the first surface of the first member to which the second member is not joined. An inter-member connection wire on the interlayer insulating film couples the first and second electronic circuits through an opening in the interlayer insulating film. A shield structure including a first metal pattern disposed on the interlayer insulating film shields a shielded circuit, which is part of the first electronic circuit, in terms of radio frequencies.Type: GrantFiled: December 13, 2021Date of Patent: October 31, 2023Assignee: Murata Manufacturing Co., Ltd.Inventors: Satoshi Goto, Masayuki Aoike, Mikiko Fukasawa
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Patent number: 11804410Abstract: A method for evaluation of thin film non-uniform stress using high order wafer warpage, the steps including measuring a net wafer warpage across a wafer area due to thin film deposition, fitting a two dimensional low-order polynomial to the wafer warpage measurements and subtracting the low-order polynomial from the net wafer warpage across the wafer area.Type: GrantFiled: March 5, 2020Date of Patent: October 31, 2023Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Wei-De Ho, Han-Wei Wu, Pei-Sheng Tang, Meng-Jung Lee, Hua-Tai Lin, Szu-Ping Tung, Lan-Hsin Chiang
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Patent number: 11804512Abstract: A light emitting stacked structure including a first epitaxial stack including a first n-type semiconductor layer, a first p-type semiconductor layer, and a first active layer disposed therebetween, a second epitaxial stack disposed on the first epitaxial stack and including a second n-type semiconductor layer, a second p-type semiconductor layer, and a second active layer disposed therebetween, a third epitaxial stack disposed on the second epitaxial layer and including a third n-type semiconductor layer, a third p-type semiconductor layer, and a third active layer disposed therebetween, and a shared electrode disposed between two adjacent epitaxial stacks facing each other, in which two semiconductor layers of the two adjacent epitaxial stacks with the shared electrode therebetween have a same polarity.Type: GrantFiled: January 4, 2021Date of Patent: October 31, 2023Assignee: Seoul Viosys Co., Ltd.Inventors: Jong Hyeon Chae, Seong Gyu Jang, Ho Joon Lee
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Patent number: 11800707Abstract: Embodiments of 3D memory devices and methods for forming the same are disclosed. In an example, a 3D memory device includes a substrate, a memory stack including interleaved conductive layers and dielectric layers above the substrate, and a channel structure extending vertically through the memory stack. The channel structure includes a high dielectric constant (high-k) dielectric layer disposed continuously along a sidewall of the channel structure, a memory film over the high-k dielectric layer along the sidewall of the channel structure, and a semiconductor channel over the memory film along the sidewall of the channel structure.Type: GrantFiled: May 22, 2020Date of Patent: October 24, 2023Assignee: YANGTZE MEMORY TECHNOLOGIES CO., LTD.Inventors: Shuangshuang Peng, Jingjing Geng, Jiajia Wu, Tuo Li
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Patent number: 11798858Abstract: A semiconductor package structure and a method of manufacturing the same are provided. The semiconductor package structure includes a first electronic component, a second electronic component, and a reinforcement component. The reinforcement component is disposed above the first electronic component and the second electronic component. The reinforcement component is configured to reduce warpage.Type: GrantFiled: July 15, 2021Date of Patent: October 24, 2023Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Meng-Wei Hsieh, Hsiu-Chi Liu
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Patent number: 11798895Abstract: A quantum device (100) includes an interposer (112), a quantum chip (111) mounted on the interposer (112), and a shield part (150) provided so as to surround a quantum circuit region of the interposer (112) and the quantum chip (111). Accordingly, the quantum device (100) is able to prevent interference in the quantum circuit region due to exogenous noise.Type: GrantFiled: June 24, 2021Date of Patent: October 24, 2023Assignee: NEC CORPORATIONInventors: Kenji Nanba, Ayami Yamaguchi, Akira Miyata, Katsumi Kikuchi, Suguru Watanabe, Takanori Nishi, Hideyuki Satou
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Patent number: 11798874Abstract: A semiconductor device includes a semiconductor chip including an electrical contact arranged on a main surface of the semiconductor chip, an external connection element configured to provide a first electrical connection between the semiconductor device and a printed circuit board, and an electrical redistribution layer extending in a direction parallel to the main surface of the semiconductor chip and configured to provide a second electrical connection between the electrical contact of the semiconductor chip and the external connection element. The electrical redistribution layer includes a ground line connected to a ground potential and a signal line configured to carry an electrical signal having a wavelength.Type: GrantFiled: November 29, 2021Date of Patent: October 24, 2023Assignee: Infineon Technologies AGInventors: Walter Hartner, Francesca Arcioni, Tuncay Erdoel, Vincenzo Fiore, Helmut Kollmann, Arif Roni, Emanuele Stavagna, Christoph Wagner
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Patent number: 11798915Abstract: Provided is a display device including a substrate including a display area including a plurality of pixel areas, and a non-display area outside the display area, a pixel circuit layer including a plurality of circuit elements in the display area, a display element layer including a plurality of light-emitting elements in the display area on the pixel circuit layer, and first and second alignment lines on the substrate, and each including a main line at the same layer as at least one electrode on the display element layer, and a sub line electrically connected to the main line and at the same layer as at least one electrode on the pixel circuit layer, wherein the first alignment line and the second alignment line do not include the main line in the non-display area, and include the sub line to be spaced apart from one edge of the substrate.Type: GrantFiled: August 11, 2022Date of Patent: October 24, 2023Assignee: Samsung Display Co., Ltd.Inventors: Sung Jin Lee, Jin Yeong Kim, Jin Taek Kim, Soo Hyun Moon, Tae Hoon Yang, Seung Min Lee
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Patent number: 11791279Abstract: A semiconductor device according to an embodiment includes a stacked body having first films and second films that are alternately stacked, a light shielding film provided in a specific layer of the stacked body and having a higher optical absorptivity than that of the second films, and a channel film extending in the stacked body in the stacking direction. The channel film includes a first part located on an upper side than the light shielding film in the stacking direction and containing a monocrystalline semiconductor.Type: GrantFiled: September 14, 2020Date of Patent: October 17, 2023Assignee: Kioxia CorporationInventors: Tatsunori Isogai, Masaki Noguchi, Tatsufumi Hamada, Shinichi Sotome
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Patent number: 11791446Abstract: A micro device includes a securing layer, a plurality of micro device units that are separated from each other and that are spaced apart from the securing layer, and a connecting layer that interconnects the micro device units in at least one group of two or more and that is connected to the securing layer so that the micro device units are connected to the securing layer through the connecting layer. A method of making the micro device is also provided.Type: GrantFiled: September 23, 2019Date of Patent: October 17, 2023Assignee: XIAMEN SAN'AN OPTOELECTRONICS CO., LTD.Inventors: Cui-Cui Sheng, Du-Xiang Wang, Bing-Xian Chung, Chun-Yi Wu, Chao-Yu Wu
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Patent number: 11791343Abstract: The disclosure provides an electronic device, which includes a substrate, two adjacent pixels, a first scan line, and two adjacent light shielding layers. The two adjacent pixels are disposed on the substrate and arranged along the first direction. A first pixel of the two adjacent pixels includes a first sub-pixel, and the first sub-pixel includes a first active region and a first conductive element electrically connected to the first active region. The first scan line is extending along the first direction. The two adjacent light shielding layers are respectively disposed between the two adjacent pixels and the substrate. The two adjacent light shielding layers are spaced apart by a first gap region, and the first gap region overlaps the first conductive element. The display device of the disclosure can reduce the problem of image quality degradation caused by photo-leakage current.Type: GrantFiled: June 22, 2022Date of Patent: October 17, 2023Assignee: Innolux CorporationInventors: Ming-Jou Tai, Chia-Hao Tsai
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Patent number: 11782284Abstract: Disclosed is a cost-effective method to fabricate a multifunctional collimator structure for contact image sensors to filter ambient infrared light to reduce noises. In one embodiment, an optical collimator, includes: a dielectric layer; a substrate; a plurality of via holes; and a conductive layer, wherein the dielectric layer is formed over the substrate, wherein the plurality of via holes are configured as an array along a lateral direction of a first surface of the dielectric layer, wherein each of the plurality of via holes extends through the dielectric layer and the substrate from the first surface of the dielectric layer to a second surface of the substrate in a vertical direction.Type: GrantFiled: August 8, 2022Date of Patent: October 10, 2023Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Hsin-Yu Chen, Yen-Chiang Liu, Jiun-Jie Chiou, Jia-Syuan Li, You-Cheng Jhang, Shin-Hua Chen, Lavanya Sanagavarapu, Han-Zong Pan, Chun-Peng Li, Chia-Chun Hung, Ching-Hsiang Hu, Wei-Ding Wu, Jui-Chun Weng, Ji-Hong Chiang, Hsi-Cheng Hsu