Abstract: A method for a computer, which is configured to access to hierarchical information indicating a hierarchical structure relating to processes executed by devices included in a network, includes receiving abnormal observation data from the network, detecting a transmission source device of the abnormal observation data and a process by which the abnormal observation data is issued, specifying a process relating, to the detected process in accordance with a kind of the detected transmission source device by referring to the hierarchical information, determining, by the computer, a failure occurrence point based on a status of the specified process.
Abstract: A disk recovery system and method is provided for recovering data from a redundant array of independent (or inexpensive) disks. The method is implemented in a computer infrastructure having computer executable code tangibly embodied on a computer readable storage medium having programming instructions. The computer readable storage medium is operable to: determine input/output (I/O) characteristics of one or more disks in an array; monitor the one or more disks in the array to determine when any of the one or more of the disks have failed in the array; and automatically rebuild the failed disk from a standby pool by nominating a disk in the standby pool based on the I/O characteristics of the one or more failed disks prior to failure.
Type:
Grant
Filed:
September 21, 2010
Date of Patent:
June 11, 2013
Assignee:
International Business Machines Corporation
Inventors:
Abhinay R. Nagpal, Sandeep R. Patil, Sri Ramanathan, Matthew B. Trevathan
Abstract: A disk array system, upon detecting a failure in any data disk from among a plurality of data disks providing one or more RAID groups, conducting a correction copy to any spare disk, using one or more other data disks belonging to the same RAID group as the data disk causing the failure. When the data disk causing the failure has been replaced with a new data disk, the disk array system alters the management so that the data disk can be managed as a spare disk, and the spare disk can be managed as a data disk.
Abstract: A method, article of manufacture, and apparatus for processing data. In some embodiments, this includes detecting a faulty interface, removing outstanding jobs from the faulty interface, distributing the outstanding jobs to other interfaces. In some embodiments, distributing the outstanding jobs includes distributing a first outstanding job to a first lowest counter interface. In some embodiments, a second outstanding job is distributed to a second lowest counter interface.
Type:
Grant
Filed:
September 30, 2010
Date of Patent:
June 4, 2013
Assignee:
EMC Corporation
Inventors:
Saradhi S. Sreegiriraju, Ornat S. Freitas
Abstract: Model-based testing is performed by repeatedly constructing a test strategy in which each test stimulus will lead to increased test coverage regardless of the nondeterministic choices made by the system under test, and following said strategy until coverage is increased. As soon as no such strategy exists, testing stops.
Abstract: A method for constructing a histogram can include sampling attributes in a column of a database on a server and determining a bucket set for the histogram based on a number of buckets that represents a distribution of the attributes with minimum error. A bucket in the bucket set includes boundaries and an approximation of a count of attributes falling within the boundaries. The method further includes determining a precision for encoding the approximation, such that the histogram having the bucket set fits within a storage limit on a tangible computer-readable medium. The histogram can then be stored for the database on a tangible computer-readable medium by encoding the approximation with the precision.
Type:
Grant
Filed:
October 26, 2010
Date of Patent:
June 4, 2013
Assignee:
Hewlett-Packard Development Company, L.P.
Abstract: A receiver apparatus can identify a plurality of patterns corresponding to scrambled synchronization bytes of a transport stream in a number of successive signal frames containing FEC code blocks, determine a pattern distribution into which most of the patterns identified in the successive signal frames map, and generate a synchronization signal locked to a distribution of the FEC code blocks associated with the pattern distribution. With this synchronization signal, FEC code blocks can be timely handled in a reliable manner through a FEC decoder, making the receiver apparatus more efficient and robust. In other embodiments, methods of handling FEC code blocks in a receiver apparatus are also described.
Abstract: A scannable integrated circuit (100) including a functional integrated circuit (P1, P2) having scan chains, multiple scan decompressors (120.1, 120.2), each operable to supply scan bits to some of the scan chains (101.k, 102.k), a shared scan-programmable control circuit (110, 300), a tree circuit (400) coupled with the functional integrated circuit (P1, P2), the shared scan-programmable control circuit (110, 300) coupled to control the tree circuit (400), and a selective coupling circuit (180) operable to provide selective coupling with the shared scan-programmable control circuit (110, 300) for scan programming through any of the multiple scan decompressors (120.1, 120.2). Other circuits, devices, systems, and processes of operation and manufacture are disclosed.
Abstract: A method for diagnosing problems in a computer system by providing a user interface for visualizing flows through subsystems of the computer system, and allowing a user to explore relationships between a triage map which graphically depicts subsystems, and a transaction trace graph, which depicts a time sequence of invoked components of the subsystems. In one aspect, in response to a user selecting a portion of the transaction trace graph which depicts an invoked component, the user interface visually distinguishes one of the subsystems which invokes the invoked component. In another aspect, the transaction trace can be played back so that subsystems in the triage map are highlighted in turn, in a time sequence, as components of different subsystems are invoked. A time marker can skip to selected time points which result in updating of the triage map.
Type:
Grant
Filed:
April 8, 2011
Date of Patent:
May 7, 2013
Assignee:
CA, Inc.
Inventors:
Laura G Beck, Natalya E Litt, Nathan A Isley
Abstract: A method for receiving a multimedia broadcast/multicast service (MBMS) is provided. The method for receiving a broadcast or multicast service includes: attempting receiving of data via a channel for the broadcast or multicast service; transmitting a negative acknowledgement to a base station if the data is not received via the channel; and receiving the data.
Type:
Grant
Filed:
June 18, 2008
Date of Patent:
May 7, 2013
Assignee:
LG Electronics Inc.
Inventors:
Young-Dae Lee, Sung-Duck Chun, Sung-Jun Park, Seung-June Yi
Abstract: In a semiconductor test apparatus, a voltage source generates a power supply voltage to be supplied to a DUT. A decision processor makes the DUT execute a predetermined test sequence. A noise generator superimposes a periodic pulse-like noise voltage on the power supply voltage to be supplied to the DUT, while the test sequence is being executed. The noise generator superimposes a noise voltage synchronized with a clock signal to be supplied to the DUT.
Abstract: A memory storage device, a memory controller, and a log likelihood ratio (LLR) generation method are provided. A read data corresponding to a first storage state is obtained from memory cells of a flash memory chip in the memory storage device by using bit data read voltages. An error checking and correcting procedure is performed on the read data to obtain a second storage state corresponding to the read data when the read data is written. An amount of storage error is obtained in storage states satisfying a statistic number, and a storage error means that data is in the second storage state when being written and is in the first storage state when being read. A logarithmic operation is executed according to the statistic number, an amount of the storage states, and the amount of storage error to generate a first LLR of the read data.
Abstract: A method and apparatus are provided for generating a parity check matrix used to generate a linear block code in a communication system. The method includes determining a basic parameter of a second parity check matrix satisfying a rule predetermined with respect to a given first parity check matrix, generating a submatrix corresponding to a parity part of the second parity check matrix, using the basic parameter; and generating a submatrix corresponding to an information word part of the second parity check matrix, using the first parity check matrix and the basic parameter.
Abstract: The present invention separates inputted triple play IP data into Internet and TV data and voice (VoIP) data, encodes the Internet and TV data permitting a long delay time according to the existing DVB-S2 standard, and encodes the voice data permitting only a short delay time according to a DVB-RCS+M standard based 4K mode. Each encoded data is subjected to the orthogonal modulation and the orthogonally modulated voice data is subjected to a direct sequence spectrum spread according to a spreading factor. The spread spectrum signal is multiplexed in a SCPC frequency division multiple access (FDMA) scheme so as to overlap with frequencies allocated to each user.
Type:
Grant
Filed:
November 5, 2010
Date of Patent:
April 16, 2013
Assignee:
Electronics and Telecommunications Research Institute
Abstract: An apparatus and method for storing data using a non-volatile buffer. A first data is stored in a first non-volatile buffer according to a first input/output request. The first data stored in the first non-volatile buffer is written into a memory cell while a second data is being stored in a second non-volatile buffer according to a second input/output request.
Abstract: Embodiments of the present invention provide novel, reliable and efficient technique for tracking, tolerating and correcting unrecoverable errors (i.e., errors that cannot be recovered by the existing RAID protection schemes) in a RAID array by reducing the need to perform drastic recovery actions, such as a file system consistency check, which typically disrupts client access to the storage system. Advantageously, ability to tolerate and correct errors in the RAID array beyond the fault tolerance level of the underlying RAID technique increases resiliency and availability of the storage system.
Abstract: Provided is a storage system, including: one or more disk drives storing data; a disk controller for controlling data access to the disk drive; a power supply controller for autonomously turning off a power source of the disk drive according to the data access status to the disk drive, and autonomously turning on the power source of the disk drive, which was turned off, after the lapse of a prescribed period from the time the power source was turned off irrespective of the data access status to the disk drive; and a media inspection unit for inspecting a failure in the disk drive in which the power source thereof was autonomously turned on irrespective of the data access status to the disk drive.
Abstract: Provided is a method in which a terminal conducts an operation for retransmission using a frame divided into downlink subframes and uplink subframes, the method including: receiving a data burst transmitted from a base station; determining a feedback frame offset based on the relationship between a range determined based on division information of the frame and a downlink subframe index in which the data burst has been transmitted; determining indices of a frame and uplink subframe for transmitting a feedback signal based on the frame offset; transmitting the feedback signal to the base station in the determined indices of the frame and uplink subframe; and if an NACK message is included in the feedback signal, receiving the data burst retransmitted from the base station.
Type:
Grant
Filed:
October 29, 2010
Date of Patent:
April 2, 2013
Assignee:
Electronics and Telecommunications Research Institute
Inventors:
Jisoo Park, Namsuk Lee, Sook Jin Lee, Yong Seouk Choi
Abstract: A circuit for detecting a fault injection in an integrated circuit including: at least one logic block for performing a logic function of said integrated circuit; an isolation block coupled to receive a signal to be processed and an isolation enable signal indicating a functional phase and a detection phase of the logic block, the isolation block applying, during the functional phase, the signal to be processed to at least one input of the logic block, and during the detection phase, a constant value to the input of the logic block; and a detection block adapted to monitor, during the detection phase, the state of the output signal of the logic block, and to generate an alert signal in case of any change in the state of the output signal.
Abstract: A method and circuit are provided for implementing switching factor reduction in Logic Built in Self Test (LBIST) diagnostics, and a design structure on which the subject circuit resides. Switching factor reduction logic is coupled to a Pseudo-Random Pattern Generator (PRPG) providing channel input patterns to a plurality of LBIST channels used for the LBIST diagnostics. The switching factor reduction logic selectively provides controlled channel input patterns for each of the plurality of channels.
Type:
Grant
Filed:
July 27, 2010
Date of Patent:
March 26, 2013
Assignee:
International Business Machines Corporation
Inventors:
Steven Michael Douskey, Ryan Andrew Fitch, Michael John Hamilton, Amanda Renee Kaufer