Abstract: A failover information management device manages information on a failover system including two storage processing devices to each of which a storage medium is connectable. The failover information management device stores unsuitability information from which a combination of two storage processing devices determined to be unsuitable for constituting the failover system is identifiable.

Abstract: A system is provided. The system detects a dropped write from a hard disk drive (HDD). The system includes two or more HDDs, each being configured to define a data block spread across the two or more HDDs. The data block is configured to regenerate a checksum across the full data block during a read operation to detect the dropped write.

Abstract: A method, data processing system, and computer program product for testing a computer system. A sequencer tests the computer system using test modules arranged in a first sequence, wherein each of the test modules is for testing at least a portion of the computer system. The sequencer determines if an operator is available, in response to an interrupt generated by a test module. If an operator is available, the sequencer arranges the test modules into a second sequence based on a first policy. If an operator is unavailable, the sequencer arranges the test modules into a third sequence based on a second policy.

Abstract: A load balancer includes a failover logic unit to identify servers to execute services, generate and store in the load balancer a failover rule and a service rule, and to determine a failure in a first server that executes a first service responsive to a lack of response by the first server to a keepalive message sent by the load balancer to the first server. The load balancer can then perform an operation to cause an automatic failover of the first service to another server based on the failover and service rules.

Abstract: A method and controller for implementing storage adapter performance optimization with a predefined chain of hardware operations configured to minimize hardware and firmware interactions and a bridge code configured to select a firmware sequence for error recovery to complete the operations responsive to an identified error in the predefined chain, and a design structure on which the subject controller circuit resides are provided. A selected predefined chain is configured to implement a particular performance path to maximize performance. Responsive to an identified predefined error during hardware operations in the predefined hardware chain, a bridge code is configured to select a non-performance path firmware sequence for error recovery completion of remaining operations.

Abstract: The present disclosure discloses a power system with hot-swap with a buck converter. The power system comprises a front stage, a hot-swap stage and a load stage; wherein the hot-swap stage comprises: a buck converter having a switch operate at ON/OFF state to provide a desired output voltage to the load stage with low power loss and optimized thermal design.

Abstract: Administering incident pools including receiving, by an incident analyzer from an incident queue, a plurality of incidents from one or more components of the distributed processing system; assigning, by the incident analyzer, each received incident to a pool of incidents; assigning, by the incident analyzer, to each incident a particular combined minimum time for inclusion in one or more pools, each particular combined minimum time corresponding to a particular incident; in response to the pool closing, determining, by the incident analyzer, for each incident in the pool whether the incident has met its combined minimum time for inclusion in one or more pools; and if the incident has been in the pool for its combined minimum time, including, by the incident analyzer, the incident in the closed pool; and if the incident has not been in the pool for its combined minimum time, including the incident in a next pool.

Abstract: A storage system comprises a first storage device having a first plurality of hard disk drives and a first controller. The first controller stores data in the first plurality of hard disk drives by stripes. Each stripe includes M data and N parity data allocated to M+N hard disk drives of the first plurality of hard disk drives. A first hard disk drive includes data or parity data of both a first stripe of the stripes and a second stripe of the stripes, while a second hard disk drive includes data or parity data of only one of the first stripe or the second stripe. During data recovery involving failure of one of the first plurality of hard disk drives, the data in the failed hard disk drive is recovered for each stripe by calculation using data and parity data in other hard disk drives for each stripe.

Abstract: Administering incident pools including receiving, by an incident analyzer from an incident queue, a plurality of incidents from one or more components of the distributed processing system; assigning, by the incident analyzer, each received incident to a pool of incidents; assigning, by the incident analyzer, to each incident a particular combined minimum time for inclusion in one or more pools, each particular combined minimum time corresponding to a particular incident; in response to the pool closing, determining, by the incident analyzer, for each incident in the pool whether the incident has met its combined minimum time for inclusion in one or more pools; and if the incident has been in the pool for its combined minimum time, including, by the incident analyzer, the incident in the closed pool; and if the incident has not been in the pool for its combined minimum time, including the incident in a next pool.

Abstract: Received communication signals may be decoded according to a combined, iterative inner code—outer code decoding technique. The inner code decoding is based on information produced by the outer code decoding.

Abstract: The present application provides a method, an apparatus and a system for memory dump processing. The method comprises: invoking a first set of processing units to process a first stage of memory dump processing for each of memory blocks; invoking each set of processing units other than the first set of processing units to process a subsequent processing stage after completing the first stage respectively, to write the memory blocks into a storage device. The technical solutions provided in the present application enable processing each stage for each of the memory blocks in a pipeline manner, avoid instantaneous peak flow of disk I/O transmission and improve memory dump performance.

Abstract: An operations management apparatus which acquires performance information for each of a plurality of performance items from a plurality of controlled units and manages operation of the controlled units includes a correlation model generation unit which derives a correlation function between a first element and a second element of the performance information, generates a correlation model between the first element and the second element based on the correlation function, and obtains the correlation model for each element pair of the performance information, and a model searching unit which searches for the correlation model for each element between an input element and an output element among elements of the performance information in series, and predicts a value of the output element from a value of the input element based on the searched correlation model.

Abstract: A method includes executing instructions recorded on a non-transitory computer-readable storage media using at least one processor. The method includes receiving a notification of a selection of an user interface (UI) element within a UI of a target application, generating a request for an element listener instance, notifying multiple test recorder hooks of the request for the element listener instance, where each of the test recorder hooks is associated with a specific UI format having multiple different element listeners depending on a type of selected UI element, creating the element listener instance by one of the test recorder hooks based on the UI format and the selected UI element, registering, by the element listener instance, for events associated with the UI element and recording the events.

Abstract: A motherboard testing device applied to a motherboard which includes two memory channels, and a CPU. Each of the two memory channels includes two memory slots. The motherboard testing device includes four memory modules received in the four memory slots, a switching chip, a microcontroller, and a testing module. The switching chip includes four input pins electrically connected to the four memory modules, four output pins electrically connected to the CPU, and a controlling pin electrically connected to the microcontroller. The microcontroller forms a plurality of combination modes of the memory slots by electrically combining the four memory slots, and controls the switching chip to electrically connect memory slots of each combination mode to the CPU. The testing module tests whether the CPU controls the memory modules received in the memory slots of each combination mode to work in proper working modes.

Abstract: A current measurement unit measuring power supply currents each consumed in a plurality of circuit blocks of which at least one of the circuit blocks includes a processor, and outputting the measurement result as the power supply current values. A selection unit selecting at least one of the power supply current values according to selection information. A trace buffer sequentially holding the power supply current values being selected by the selection unit together with execution information of the processor, and sequentially outputting the held information. By selecting the power supply current values of the circuit blocks required for debugging according to the selection information, the number of external terminals of a semiconductor integrated circuit required for the debugging which includes tracing the power supply current values may be reduced. As a result, a chip size of the semiconductor integrated circuit with a debug function may be reduced.

Abstract: According to one embodiment, a disk storage apparatus includes a write module, an operation module, and a controller. The write module is configured to write data, in units of blocks, in a designated write area of a disk. The operation module is configured to perform an exclusive OR operation on the blocks of data. The controller is configured to control the write module, causing the write module to write, in a designated block, recovery data that is a result of the exclusive OR operation on all data blocks written in the designated write area.

Abstract: Methods and structure for providing methods and structure for recovering errors in a hardware controller after an overwrite event, such as the detection of another error. In this regard, a link layer of the hardware controller is configured with a register that persistently stores errors until a processor can address them. The link layer is adapted to establish a connection between an initiator and a target and detect errors associated with the connection. As each detected error is overwritten by a subsequently detected error, the link layer register persistently stores the detected errors associated with the connection for recovery after the detected error has been overwritten in the link layer at least until the error can be handled.

Abstract: Methods and apparatus for providing continuous availability include communicatively coupling a first node and a second node, each having at least one processor, an executing application management framework, and a first application. The first node is executing its associated first application. A plugin for the first node application management framework is executed. The plugin is dynamically loadable by the application management framework. The plugin specifies application availability rules for protecting the availability of the first application.

Abstract: A system and method of identifying a memory includes detecting defects in regions of the memory, comparing the detected defects with defects contained in a previously-created defect map associated with the memory and stored in another memory of a device accessing the memory, confirming the identity of the memory where a result of the comparison indicates the detected defects match defects contained in the previously-created defect map; and denying the identity of the memory where the result of the comparison indicates the detected defects do not match the defects contained in the previously-created defect map.

Abstract: Systems, methods, and computer program products are provided for instant recovery of a virtual machine (VM) from a compressed image level backup without fully extracting the image level backup file's contents to production storage. The method receives restore parameters and initializes a virtual storage. The method attaches the virtual storage to a hypervisor configured to launch a recovered VM. The method stores virtual disk data changes inflicted by a running operating system (OS), applications, and users in a changes storage. The method provides the ability to migrate the actual VM disk state (taking into account changed disk data blocks accumulated in changes storage) so as to prevent data loss resulting from the VM running during the recovery and accessing virtual storage, to production storage without downtime. In embodiments, the method displays receives restore parameters in an interactive interface and delivers the recovery results via an automated message, such as an email message.