Abstract: The present solution provides increases in automation, scalability and efficiency for delivering technical support services to devices. Systems and methods of the present solution provide a hierarchy or layers of automated desktop services with remote technical support services, which may be automated. The present solution provides an on desktop automation support system that detects and automatically remediates problems on a device of the user. If the problem is not fixed or fixable via local automated remediation at the desktop, a centralized service may remotely deliver technical support services to the device in the form of automated support services delivered to the device or remote technical agents connecting remotely with the device. With the combination of local support automation, remote support automation, remote and onsite technicians, the centralized service may deliver a hierarchy or multi-layers of services to any device.

Abstract: Technology for identifying virtual computing instance issues is described. An operating information report of a virtual computing instance may be parsed to obtain a diagnostic result. The diagnostic result may be compared against a data store of known computing instance issues to determine whether there is an issue for the virtual computing instance. The issue may be flagged when identified and provided for resolution.

Abstract: A system and method of identifying a memory includes detecting defects in regions of the memory, comparing the detected defects with defects contained in a previously-created defect map associated with the memory and stored in another memory of a device accessing the memory, confirming the identity of the memory where a result of the comparison indicates the detected defects match defects contained in the previously-created defect map; and denying the identity of the memory where the result of the comparison indicates the detected defects do not match the defects contained in the previously-created defect map.

Abstract: Techniques for blacklisting of fault generating software code are provided. An example method includes receiving crash reports of a plurality of browsers, a crash report including an identification of one or more executables related to a software crash of a browser, wherein software code of the executables is included in a memory space of the browser during the software crash, analyzing the crash reports of the browsers to determine a browser component affected by software code of an executable included in respective memory spaces of the browsers to cause one or more software crashes of the browsers, computing, for the executable, a fault level based on a number of crashes of the browser component that is associated with the executable and a number of crashes of the browser component independent of the executable, and including an identifier representing the executable in a list based on the determined fault level.

Abstract: A method for automated detection of a real IT system problem may include obtaining monitor measurements of metrics associated with activities of a plurality of configuration items of the IT system. The method may also include detecting anomalies in the monitor measurements. The method may further include grouping concurrent anomalies of the detected anomalies corresponding to configuration items of the plurality of configuration items which are topologically linked to be regarded as a system anomaly. The method may further include calculating a significance score for the system anomaly, and determining that the system anomaly relates to a real system problem based on the calculated significance score.

Abstract: A debug control system and method thereof which includes a debug device and a wireless communication module. The debug device is configured to communicate electrical data with a target device via a first signal transmission interface. The wireless communication module is configured to communicate electrical data with the debug device via a second communication interface, and is configured to communicate electrical data with a host device. Electrical data exchanged between the debug control system and the target device is configured to debug or update firmware residing on the target device.

Abstract: A solid state drive (SSD), includes: a plurality of solid state memory devices, each solid state memory device including a plurality of memory blocks arranged in a plurality of planes; a storage; and an SSD controller configured to: write data to memory blocks in a predefined sequence, detect a defective memory block in the plurality of solid state memory devices, mark the detected memory block as defective and store an address of a next non-defective memory block, and in response to data to be written to the marked memory block, the controller skips the marked memory block and writes the data to the next non-marked memory block.

Abstract: A method for updating firmware in a user terminal comprises dividing files with modified contents into a plurality of groups and assigning each file with respective offset. The method then performs bitwise XOR operations between the plurality of groups onto the backup buffer. Consequently, the method stores a result of the bit XOR operations on the backup buffer into a non-volatile storage as a backup file. An apparatus for updating firmware comprises a processing circuit configured to divide files with modified contents into a plurality of groups and assign each file with respective offset. The processing circuit performs bitwise XOR operations between the plurality of groups onto the backup buffer and store a result of the bit XOR operations on the backup buffer into a non-volatile storage as a backup file.

Abstract: An apparatus and method for error management in an integrated circuit system are presented. An error management unit (EMU) apparatus manages critical and non-critical errors that may be masked or non-masked. An EMU includes an EMU state machine, having a BOOT state, a CONFIG state, a FUNCT state, a WARNING state and an ERROR state. The method discloses transitions in the EMU state machine. While in the ERROR state an error reaction may be applied. The objective of the error reaction is to recover errors by software and hardware means. The EMU may further appropriately alert the system while in ERROR state and therefore be used as a safety mechanism permitting to collect error signals issued by fault detector units and can further cause action on faulty units for recovery purposes.

Abstract: Methods and systems for generating data transformations to improve ROM yield and programming time. A bit flip register can be configured in association with the ROM and a binary string can be read into the bit flip register on reset. Subsequently, data output from the ROM can be selectively complemented utilizing a content of the bit flip register and the content of the bit flip register can be programmed into the ROM in order to reduce programming time for each ROM. A defective cell can be tolerated by selectively flipping a column with respect to the defective cell to improve yield. A built-in self-test (BIST) engine that generates addresses up to and including content of an address limiting register can be employed to limit the ROM access to a programmed part during testing in order to tolerate defects in any unused location.

Abstract: A current measurement unit measuring power supply currents each consumed in a plurality of circuit blocks of which at least one of the circuit blocks includes a processor, and outputting the measurement result as the power supply current values. A selection unit selecting at least one of the power supply current values according to selection information. A trace buffer sequentially holding the power supply current values being selected by the selection unit together with execution information of the processor, and sequentially outputting the held information. By selecting the power supply current values of the circuit blocks required for debugging according to the selection information, the number of external terminals of a semiconductor integrated circuit required for the debugging which includes tracing the power supply current values may be reduced. As a result, a chip size of the semiconductor integrated circuit with a debug function may be reduced.

Abstract: Methods, apparatuses, and computer program products for determining whether to send an alert are provided. Embodiments include a voting manager receiving from a plurality of alert analyzers, one or more delivery codes associated with an alert. In dependence upon the one or more delivery codes, the voting manager determines whether to suppress the alert, to close the alert, or to report the alert.

Abstract: A processing unit of the embodiments includes an instruction memory that holds a plurality of instructions specified by addresses, and that cannot execute read and write operations concurrently, an error correction circuit that detects and corrects an error in the instruction, a program counter, an instruction buffer that holds the instruction corrected as a corrected instruction, a program counter buffer that holds an address of the instruction where an error has been detected, a selector that selects and outputs any of the output of the error correction circuit and the output of the instruction buffer, and a control unit that controls the read and write of the instruction specified by the address from and into the instruction memory. The control unit writes the corrected instruction in the instruction memory using an address held in the program counter buffer when a predetermined condition is satisfied after the occurrence of the error.

Abstract: The present invention discloses a management module for a storage device. The management module comprises a primary server and a secondary server. Each server comprises a network port configured to interface the server and a telecommunication network and a virtual bridge configured to selectively enable or disable data transfer to and from the network port. The virtual bridges of the primary and secondary servers are linked for enabling data transfer between said virtual bridges, the virtual bridge of the primary server is configured to disable data transfer while the virtual bridge of the secondary server is configured to enable data transfer and the virtual bridge of the primary server is further configured to maintain an IP address of the management module.

Abstract: In a testing device, a method for implementing distributed pin mapping. The method includes receiving a request from a plurality of CPUs to access a pin map memory at each of a plurality of bridges, implementing accesses to the pin map memories locally at each of the plurality of bridges, and using pin map data from the accesses to the plurality of CPUs to enable access to testing device resources.

Abstract: A test device is provided for testing a device under test (DUT) having a control interface compliant with a standard selected from a plurality of standards each supporting a common set of management data input/output (MDIO) and non-MDIO control signals. The test device includes a test interface and an integrated control interface. The integrated control interface adapts to the standard with which the control interface of the DUT complies, so that the integrated control interface directly and fully controls the DUT via at least the common set of MDIO and non-MDIO control signals. The integrated control interface exchanges control signals selected from the common set of MDIO and non-MDIO control signals with the control interface of the DUT to monitor the DUT and thereby obtain status information about the DUT.

Abstract: Systems and methods to detect errors and record actions on a bus are disclosed. In one embodiment, the bus is a serial low-power interchip media bus (SLIMbus) within a computing device. The SLIMbus is coupled to peripherals and a sniffer is positioned within the computing device and coupled to the SLIMbus. The sniffer mimics another SLIMbus peripheral. However, the sniffer uses a pair of multiplexers to know when to record data on the SLIMbus. The data, including the control header and payload of the data signal is captured and logged. The logged data is then exported to memory where it can be further processed so as to help debug communication on the SLIMbus.

Abstract: Some embodiments include apparatuses and methods having a first interface to communicate with a processing unit, a second interface to communicate with a memory device, and a module coupled to the first and second interfaces. In at least one of the embodiments, the module can be configured to obtain information stored in the memory device and perform at least one of testing and repairing of a memory structure of the memory device based at least in part on the information.

Abstract: A system to recover a multimaster serial single-ended bus and a faulted connected device includes a director device connected to the faulted connected device via the multimaster serial single-ended bus. The director device includes a central processing unit, a field programmable gate array, and a management module in communication with the faulted connected device, the management module configured to recover the faulted connected device and the multimaster serial single-ended bus. The management module may transmit a clock pulse to the faulted connected device if the faulted connected device is holding a data line (SDA) low, transmit a stop command to the faulted connected device if the faulted connected device is holding SDA low and/or read and compare a register value in the faulted device against an expected value to determine if the faulted device and the multimaster serial single-ended bus have been recovered.

Abstract: An apparatus for preventing a malfunction of a peripheral device in a portable terminal with multiple processors includes a battery, a peripheral device electrically connected to a switch through a I/O pins, a first processor in which a control port for the peripheral device is electrically connected to the switch through the GPIO method, and which controls driving of the peripheral device through generation of a normal high signal, a second processor electrically connected to the switch through the GPIO method, and the switch driven by the battery, configured to operate such that the control port of the first processor is grounded when it is determined that an unintended high signal is generated from the second processor before the portable terminal is completely booted.