Abstract: A computer implemented method for temporal ranking in invariant networks includes considering an invariant network and a set of broken invariants in the invariant network, assuming, for each time point inside a window W, that each metric with broken invariants is affected by a fault at that time point, computing an expected pattern for each invariant of a metric with assumed fault, said pattern indicative of time points at which an invariant will be broken given that its associated metric was affected by a fault at time t, comparing the expected pattern with the pattern observed over the time window W; and determining a temporal score based on a match from the prior comparing.

Abstract: A system and method for verifying computation output using computer hardware are provided. Instances of computation are generated and processed on hardware-based processors. As instances of computation are processed, each instance of computation receives a load accessible to other instances of computation. Instances of output are generated by processing the instances of computation. The instances of output are verified against each other in a hardware based processor to ensure accuracy of the output.

Abstract: In a processing system comprising a plurality of data processors at an integrated circuit die, each data processor has a local debug module. In response to acquiring data trace information based upon a corresponding local filtering criteria, the local debug modules transmit their data trace information to a global resource from each of the local debug modules for further filtering by a common filtering criteria.

Abstract: Apparatuses and methods associated with memory allocations for virtual machines are disclosed. In embodiments, an apparatus may include a processor; a plurality of memory modules; and a memory controller configured to provide a layout of the memory modules. The apparatus may further include a VMM configured to be operated by the processor to manage execution of a VM by the processor including selective allocation of the memory modules to the VM using the layout of the memory modules provided to the VMM by the memory controller. Other embodiments may be described and claimed.

Abstract: A memory subsystem includes a test signal generator of a memory controller that generates a test data signal in response to the memory controller receiving a test transaction. The test transaction indicates one or more I/O operations to perform on an associated memory device. The test signal generator can generate data signals from various different pattern generators. The memory controller scheduler schedules the test data signal pattern, and sends it to the memory device. The memory device can then execute I/O operation(s) to implement the test transaction. The memory controller can read back data written to a specific address of the memory device and compare the read back data with expected data. When the read back data and the expected data do not match, the memory controller can record an error. The error can include the specific address of the error, the specific data, and/or encoded data.

Abstract: A method of determining whether a set of constraints is satisfiable may include identifying a set of constraints associated with a software module. The method may also include modeling a string associated with a string constraint of the set of constraints as a parameterized array. Further, the method may include determining the satisfiability of the set of constraints based on a representation of the string constraint as a quantified expression. The satisfiability of the set of constraints may also be based on elimination of a quantifier associated with the quantified expression such that the string constraint is represented as a numeric constraint. The representation of the string constraint as a quantified expression may be based on the parameterized array that is associated with the string.

Abstract: A processor includes an execution unit, a fault mask coupled to the execution unit, and a suppress mask coupled to the execution unit. The fault mask is to store a first plurality of bit values to indicate which elements of a multi-element vector have an associated fault generated in response to execution of an instruction on the element in the execution unit. The suppress mask is to store a second plurality of bit values to indicate which of the elements are to have an associated fault suppressed. The processor also includes counter logic to increment a counter in response to an indication of a first fault associated with the first element and received from the fault mask, and an indication of a first suppression associated with the first element and received from the suppress mask. Other embodiments are described as claimed.

Abstract: A communication system includes a switch that switches output ports according to an address of transmission data; a storing unit that stores a first set of addresses associated with the switch; a determining unit that determines, when a second set of addresses including in the transmission data a response to which is not received matches the first set of addresses in the storing unit, that there is a failure in the switch associated with the first set of addresses.

Abstract: In a data processing system, a selection is made, based at least on an access type of a memory access request, between at least a first timing and a second timing of data transmission with respect to completion of error detection processing on a target memory block of the memory access request. In response to receipt of the memory access request and selection of the first timing, data from the target memory block is transmitted to a requestor prior to completion of error detection processing on the target memory block. In response to receipt of the memory access request and selection of the second timing, data from the target memory block is transmitted to the requestor after and in response to completion of error detection processing on the target memory block.

Abstract: In a data processing system, a selection is made, based at least on addresses of previously detected errors in a memory subsystem, between at least a first timing and a second timing of data transmission with respect to completion of error detection processing on a target memory block of the memory access request. In response to receipt of the memory access request and selection of the first timing, data from the target memory block is transmitted to a requestor prior to completion of error detection processing on the target memory block. In response to receipt of the memory access request and selection of the second timing, data from the target memory block is transmitted to the requestor after and in response to completion of error detection processing on the target memory block.

Abstract: In a data processing system, a selection is made, based at least on addresses of previously detected errors in a memory subsystem, between at least a first timing and a second timing of data transmission with respect to completion of error detection processing on a target memory block of the memory access request. In response to receipt of the memory access request and selection of the first timing, data from the target memory block is transmitted to a requestor prior to completion of error detection processing on the target memory block. In response to receipt of the memory access request and selection of the second timing, data from the target memory block is transmitted to the requestor after and in response to completion of error detection processing on the target memory block.

Abstract: An apparatus and computer-implemented method for determining relevance of assignments in combinatorial models, the method comprising: receiving an attribute collection, the attribute collection comprising one or more attributes and one or more possible values for each of attributes; receiving pone or more restrictions, each restriction indicating one or more values for one or more attributes; receiving one or more assignments comprising one or more assigned values for one or more of the attributes; and determining whether the assignment is legal, illegal or partially-legal, wherein an illegal assignment is an assignment which violates a constraint by itself; a legal assignment is an assignment which is not illegal, and for every extension thereof which is illegal, a combination of values assigned to other attributes violates a constraint by itself; and a partially-legal assignment is an assignment which is neither legal nor illegal.

Abstract: During a debug mode of operation of a data processor it is determined whether a data access request is to a stack of the data processor. If not, a data trace message based on the data access request is generated for transmission to a debugger so long as an address being accessed by data access request meets a predefined address range criteria. Otherwise, if the data access request is to the stack of the data processor, a data trace message based on the data access request is prevented from being generated for transmission to the debugger regardless the predefined address range criteria.

Abstract: A system, and in particular a system operating in real-time, may have its operation rely on a particular sequence of trigger signals, hardware or software, for proper operation. A trigger sequence checker provides a way to monitor in real-time predetermined sequences of triggers and is configured to generate an error signal upon detection of a faulty operation or sequence. Rules for sequences of triggers are stored in memory and are used by the trigger sequence checker to verify one or more sequences of triggers received as an input to the checker. A plurality of triggers may be handled by the checker. In one embodiment the checker is configurable to be set in a learning mode to capture triggers rules.

Abstract: A disaster recovery appliance is described herein. The disaster recovery appliance is coupled to one or more servers. The disaster recovery appliance continuously receives backup data for each of the one or more servers. When a server fails, the disaster recovery appliance, replaces the failed server. While the failed server is inaccessible, the disaster recovery appliance is able to mimic the functionality of the failed server. In some embodiments, the disaster recovery appliance is able to act as a server in addition to a backup device for the other servers.

Abstract: A method, article of manufacture, and apparatus for restoring data. In some embodiments, this includes determining an object to be recovered, determining a representation of the object, and requesting the representation of the object from a data resource system. In some embodiments, the representation of the object is a hash value of the object. In some embodiments, the representation of the object is a segment of the object.

Abstract: A data migration operation uses an error flag to protect against data corruption. During write cloning states, the error flag is set and only allowed state transitions are performed, including a non-error transition to a committed state when no device fault is recorded for a target storage device and an error transition to a setup state when a device fault is recorded for the target storage device. In a clean system shutdown, a shutdown procedure records a detected target storage device fault and clears the error flag; the recorded device fault later forces the error transition of the migration operation. During the system startup, if the error flag is set then a target storage device fault is recorded to likewise later force the error transition of the migration operation, on the assumption that a detected fault may exist but be unrecorded because the shutdown procedure did not complete during shutdown.

Abstract: Disclosed is a method to enable wireless remote session recovery for a wireless device. Should a wireless device encounter a broken communication link during a virtual mobile management (VMM) operation, a method of automatic session recovery is disclosed which executes from a management console through a communication end-point gateway server in order to reconnect the mobile device. Under control of the session reconnection method, the device client listener and tools of wireless device re-establishes the signal and bearer links with a management console, over the air through the communication end-point gateway server (CEG). The communication utilizing the session recovery algorithm enables the wireless device to receive session information from the communication end-point gateway server, including the respective tools.

Abstract: During starting of a field device for pressure measurement, flow measurement and/or fill level measurement, which field device including a memory that includes a boot memory region in which a boot function is stored, and an operating memory region in which an operating function is stored, the following steps are carried out: carrying out the boot function; determining whether a memory check of the operating memory region is to be carried out; carrying out a memory check of the operating memory region when it has been determined that a memory check is to be carried out; and carrying out the operating function.

Abstract: Multiple storage apparatuses are provided, at least part of which are individually incorporated into one of storage groups. Each of multiple control apparatuses is configured to, when assigned one or more of the storage groups each including one or more of the storage apparatuses, control data storage by storing data designating each assigned storage group redundantly in the storage apparatuses of the assigned storage group. An information processing apparatus is configured to, when a storage group with data redundancy being lost is detected, make a change in control apparatus assignment for the storage groups in such a manner that a storage group different from the detected storage group is not assigned to a control apparatus with the detected storage group assigned thereto. Subsequently, the information processing apparatus causes the control apparatus to execute a process of restoring the data redundancy of the detected storage group.