Patents Examined by Dieu-Minh T. Le
-
Patent number: 6012143Abstract: In a card-type storage medium and transaction apparatus, when a transaction is started between the card-type storage medium and the transaction apparatus and a data file that is an object of an access from the transaction apparatus is determined, a unique identifier generating device of the card-type storage medium generates a unique identifier for this transaction. A unique identifier notifying device notifies the unique identifier to the transaction apparatus. Accordingly, it is possible to specify the transaction apparatus having access to the card-type storage medium by referring to that unique identifier.Type: GrantFiled: October 30, 1996Date of Patent: January 4, 2000Assignee: Fujitsu LimitedInventor: Hiroshi Tanaka
-
Patent number: 6009527Abstract: Security from an unwanted intrusion into a computer system is provided by coupling a host component with a peripheral component using a high-speed serial bus having a high-speed physical layer and using features of the bus to implement the security. In an embodiment, the high-speed serial bus has a secondary bus layer that is used to implement a number of the security features of the invention.Type: GrantFiled: October 23, 1997Date of Patent: December 28, 1999Assignee: Intel CorporationInventors: C. Brendan S. Traw, Eric C. Hannah, Jerrold V. Hauck, Richard L. Coulson, Brad W. Hosler
-
Patent number: 6009528Abstract: A communication system includes a communication apparatus for connecting a first network to a second network, wherein a packet transmitted by a transmitting station in the first network by way of the communication apparatus to a receiving station in the second network is relayed selectively by the communication apparatus to the second network. First authentication information is created, in part, according to predetermined key information and the packet is transmitted with the header information thereof including the first authentication information. First authentication information in the header information of the packet is compared with second authentication information created, in part, according to predetermined key information, by the communication apparatus in order to determine whether or not the packet is to be relayed to the second network.Type: GrantFiled: December 30, 1996Date of Patent: December 28, 1999Assignee: Sony CorporationInventor: Fumio Teraoka
-
Patent number: 6009540Abstract: A system, method and apparatus including a logic module, preferably embodied as an electronic card that operates in combination with a PC to correct errors caused by deficiencies existing in logic residing on the PC's motherboard, such as the PC's BIOS. The preferred logic card includes a transceiver module, a memory module (e.g. an EPROM or Masked ROM) containing storage elements and executable code stored as pages. The preferred logic card also includes a page register module in communication with the transceiver and the memory, and a paging mechanism that cooperates with the page register and the transceiver for allowing only a predetermined number of bytes (pages) of executable code to be accessible for operation in the PC's main-memory in order to correct errors caused by deficiencies existing in logic residing on the PC's motherboard.Type: GrantFiled: April 8, 1997Date of Patent: December 28, 1999Assignee: AITM Associates IncorporatedInventors: Thomas W. Craft, Donald Lee Dobbs
-
Patent number: 6009538Abstract: A system and method of reporting a status of another system through an electronic price label (EPL). The system includes the EPL and a computer coupled to the EPL which monitors the status of the second system and causes the EPL to display a status message indicating the status of the second system. The second system may include a POS system, credit authorization system, or any other in-store system.Type: GrantFiled: April 22, 1997Date of Patent: December 28, 1999Assignee: NCR CorporationInventors: John C. Goodwin, III, Andrew J. Adamec, Cheryl K. Harkins
-
Patent number: 6006344Abstract: A personal computer system is discloses which includes a diagnostic system which uses an input/output controller to perform diagnostic functions. Such a system advantageously allows diagnostic functions to be performed on the computer system including the system processor of the computer system. The diagnostic program may be stored within nonvolatile memory which is coupled to the I/O controller, thus allowing diagnostic functions to be performed without the need for the computer system memory of the computer system.Type: GrantFiled: January 21, 1997Date of Patent: December 21, 1999Assignee: Dell USA, L.P., A Texas Limited PartnershipInventor: Joseph W. Bell, Jr.
-
Patent number: 6000046Abstract: A system uses a common error processing process within a computer system wherein other processes that detect errors send an error message to the common process and the common process is used to display all error messages, and display the help file. The common error process detects whether the system is a distributed application running on multiple computer systems, and if this is so, the common error process sends any error messages to other computers within the distributed network, so that the error messages are displayed on all computers when one computer has an error. The system reserves an amount of memory when it is started, and keeps this memory reserved throughout operation of the system. If an out of memory error occurs in a process, the reserved memory is released, to provide sufficient memory for building an error message.Type: GrantFiled: January 9, 1997Date of Patent: December 7, 1999Assignee: Hewlett-Packard CompanyInventor: Carole J. Passmore
-
Patent number: 5996109Abstract: An error detection and correction device in which a word train including a number of error correction codes each constructed from a plurality of words is input, the error correction code being of the type that two error words can be corrected by each error correction code. Error words are corrected by using the error correction code within the word train. Mode setting information associated with an error rate of the word train is generated, and an error correction means is controlled in a first or a second error correction mode depending on the mode setting. The error correction means corrects one or two error words for each error correction code in the first error correction mode and corrects only one error word for each error correction code in the second error correction mode.Type: GrantFiled: July 17, 1997Date of Patent: November 30, 1999Assignee: Canon Kabushiki KaishaInventor: Akihiro Shikakura
-
Patent number: 5996091Abstract: A method for programming or testing a CPLD using an additional read register. In one embodiment, the method comprises: instructing the CPLD in one instruction to load program data, load address information and program the program data into a memory location having an address defined by the address information; loading the program data into a first data storage element and the address information into an address storage element; programming the program data into the memory location; instructing the CPLD to read verify data from the memory location; and capturing the verify data into a second data storage element. The second data storage element comprising a read registers. The novel method further comprises comparing the verify data with the program data. The verify data and the program data may be compared within the CPLD or the verify data may be output from the CPLD and compared with the program data externally.Type: GrantFiled: August 19, 1997Date of Patent: November 30, 1999Assignee: Cypress Semiconductor Corp.Inventors: Christopher W. Jones, David L. Johnson
-
Patent number: 5996093Abstract: A method and a device for determining that digital information written into a memory is correctly readable before such read information, in the form of a number of coordinated bit positions, is used to control one or several functions, where the functions can be activated by a computer unit. A selected address position or positions within the memory corresponding to the stored digital information points out a first set of bits, required to control and/or initiate the functions, and a second set of bits serving as a control sum. The second set of bits is calculated taking into consideration the current set of bits corresponding to the first set of bits and a third set of bits, corresponding to the address position currently selected for readout.Type: GrantFiled: March 28, 1997Date of Patent: November 30, 1999Assignee: Telefonaktiebolaget LM EricssonInventor: Leif Mikael Larsson
-
Patent number: 5987607Abstract: The present invention aims to provide a system, which can prevent unauthorized copying of information in a society covered by a network and can exclude distribution and diffusion of information in the network or package media. In a system comprising a receiving unit connected to broadcasting and/or communication network, there are provided a transmitting unit, a writing unit to a package medium, a reading unit, a reproducing unit for displaying and reproducing the information, and a management unit including a filing unit, each of these units has an ID to define a space to which that unit belongs, and by comparing it with a space ID, which defines a space where the information can be utilized and is added to the information transferred within the system, the compatibility of the utilization, i.e. whether the information is being utilized in an authorized space or not, is checked and unauthorized utilization of information or unauthorized copying are prevented.Type: GrantFiled: April 2, 1997Date of Patent: November 16, 1999Assignee: Matsushita Electric Industrial Co., Ltd.Inventor: Tomoki Tsumura
-
Patent number: 5983369Abstract: An online computer support system uses simultaneous and alternating transfer of different data types including voice, image, video, and other digital information. This allows a customer service representative and a user having a computer problem to communicate more effectively and solve the problem. The customer service representative can provide prepared tutorials or information to the customer in the form of text, diagrams, and video with synchronized sound. Software at the user computer side automatically interrogates the user computer to determine information about hardware and software components needed to solve problems the user is having. Information, such as the serial number, is programmed into non-volatile memory at the factory for reading during, or at the beginning of, an online support session. The customer service representative can control the user's computer remotely. Software agents are used to perform specific functions.Type: GrantFiled: June 17, 1996Date of Patent: November 9, 1999Assignees: Sony Corporation, Sony Electronics Inc.Inventors: Brian Bakoglu, Parichay Saxena
-
Patent number: 5983365Abstract: To test the processing of a data frame processing unit (FPU) which, in a normal working mode, processes input data frames applied to a data frame input (FI) thereof, the data frame processing unit (FPU) is brought in a test mode. Therefore, an active test signal is applied to a test mode control input (TCI) of this data frame processing unit (FPU). When brought in the test mode, the frame counters of the data frame processing unit (FPU) have lower limits and test data frames with smaller dimensions than the input data frames applied to the data frame input (FI).Type: GrantFiled: February 15, 1996Date of Patent: November 9, 1999Assignee: Alcatel N.V.Inventors: Daniel Frans Jozefina Van de Pol, Erik Moerman, Johan David, Johannes Anthonius Maria Van Tetering
-
Patent number: 5974570Abstract: A method of managing a memory area, in a data processing system, comprising providing a managing information memory area for items of in use, test done, and temporary fault of pages in a page table for managing a memory unit. In accordance with such a scheme, when a page is allocated to a program, an operation test is conducted on a page not tested, the time when the operation test has been conducted is recorded, and an operation test is again conducted on a page for which a predetermined time has passed since the last test performed thereat. Also, the values of output signals of main and sub memory modules of the data processing system are compared while the data processing system is operating, and if a difference is found, that is, non-coincidence is detected, this difference is detected as a fault by the test.Type: GrantFiled: February 28, 1996Date of Patent: October 26, 1999Assignee: Hitachi, Ltd.Inventors: Atsuo Kawaguchi, Hiroshi Motoda
-
Patent number: 5974568Abstract: Error reporting may be enhanced, by utilizing a programming language, such as C++ and its attendant enhanced error reporting facility. The invention generates an error message at the function level where the error occurs, as well as noting the line of source code during which time the error occurred. The resulting populated error message is then rolled up toward the main program. At each preceding roll up level, an additional error message is populated which notes the original error message information as well as adding return path information. Thus, after completed roll up to the main program, stacked error messages are made available to the user that fully define the complete path involving the error, in addition to the identification of the source code line where the error occurred.Type: GrantFiled: November 17, 1995Date of Patent: October 26, 1999Assignee: MCI Communications CorporationInventor: Stan McQueen
-
Patent number: 5974562Abstract: A network management system includes a main network management station and a backup network management station. Different physical and logic addresses are assigned to the two stations. The data packet(s) containing network management information has/have the physical and logical addresses assigned to the main network management station. Thus, only the main network management station can receive the data packet(s) containing network management information when it is in a proper operational condition. When the main network management station is about to fail, a packet (or packets) containing operational status information is/are sent to the backup network management work station, via a network. Upon receiving the operational status information, the physical and logical addresses assigned to the backup network management work station is modified as the physical and logical addresses assigned to the main network management station.Type: GrantFiled: December 5, 1995Date of Patent: October 26, 1999Assignee: NCR CorporationInventors: Robert L. Townsend, Luo-Jen Chiang
-
Patent number: 5968187Abstract: Disclosed is a computer system and method in which a portable portion has the capability to diagnose and perform analysis for the stationary portion and for the portable portion. The computer system includes a portable computer having a network interface circuit coupled between the portable computer and a network. The network interface circuit includes a processor and a network address logic for identifying a network address associated with the portable computer. A stationary computer includes a network interface circuit coupled between the stationary computer and the network. The network interface circuit of the stationary computer sends an instruction set to the network interface circuit of the portable computer via the network based on the network address associated with the first computer. The processor on the network interface circuit of the portable computer executes the instruction set of performed diagnoses for the portable computer.Type: GrantFiled: April 28, 1997Date of Patent: October 19, 1999Assignee: NCR CorporationInventor: Michael G. Robinson
-
Patent number: 5968175Abstract: A software use method control system including a storage device and an access controller. The storage device stores information for designating a right to access system resources of operating systems which are to be executed in the software use method control system. The access controller controls access to the system resources of the operating systems. The system also includes a privilege protecting section. The privilege protecting section includes an input receiver for receiving an execution request made by a software user, a program-executing device for executing a program having a right to access all system resources of the operating systems, and a program-execution inhibiting device for determining whether the program-executing device is allowed to executed the program, from the execution request which the input receiver has received, and for inhibiting the program executing device from executing the programs when the programs are not allowed to be executed.Type: GrantFiled: June 23, 1997Date of Patent: October 19, 1999Assignee: Kabushiki Kaisha ToshibaInventors: Akira Morishita, Miwako Doi, Seiji Miike, Hirofumi Muratani
-
Patent number: 5964877Abstract: A security system for protecting a protected device including control circuitry, a non-volatile memory, a data transceiver, and input keys. A remote activation unit, including a non-volatile memory, data transceiver, and input key, is used to access the protected unit by communicating a code stored in the memory of the activation unit to the protected unit via data transceivers. If the activation unit is lost or the user desires to change the password, the user may enter a new password using the input keys of the protected unit, which is then stored in the non-volatile memory of the protected unit. The user may then initiate a password programming operation, which would involve the communication of the new password entered by the user to the remote activation unit via the data transceivers. Once the remote activation unit receives the new password, it would then store the new password in the non-volatile memory of the activation unit.Type: GrantFiled: April 7, 1997Date of Patent: October 12, 1999Inventors: David William Victor, David Ian Reiner
-
Patent number: 5961653Abstract: An integrated chip having a DRAM embedded in logic is tested by an in-situ processor oriented BIST macro. The BIST is provided with two ROMS, one for storing test instructions and a second, which is scannable, that provides sequencing for the test instructions stored in the first ROM, as well as branching and looping capabilities. The BIST macro has, in addition, a redundancy allocation logic section for monitoring failures within the DRAM and for replacing failing word and/or data lines. By stacking the DRAM in 0.5 mb increments up to a 4.0 mb maximum or in 1.0 mb increments up to an 8 mb maximum, all of which are controlled and tested by the BIST macro, a customized chip design with a high level of granularity can be achieved and tailored to specific applications within a larger ASIC.Type: GrantFiled: February 19, 1997Date of Patent: October 5, 1999Assignee: International Business Machines CorporationInventors: Howard Leo Kalter, John Edward Barth, Jr., Jeffrey Harris Dreibelbis, Rex Ngo Kho, John Stuart Parenteau, Jr., Donald Lawrence Wheater, Yotaro Mori