Patents Examined by Dieu-Minh T. Le
  • Patent number: 6073243
    Abstract: A flash memory device including a first memory array, block locking circuitry, and control circuitry. The memory array includes a plurality of memory blocks each having a memory cell. The block locking circuitry includes a plurality of block lock-bits and a master lock-bit. Each block lock-bit corresponds to one of the plurality of memory blocks and indicates whether the corresponding memory block is locked. The master lock-bit indicates whether the plurality of block lock-bits are locked. The control circuitry is configured to receive a passcode that causes the control circuitry to override the master lock-bit. The control circuitry may also be configured to receive a passcode that causes the control circuitry to override one of the block lock-bits.
    Type: Grant
    Filed: February 3, 1997
    Date of Patent: June 6, 2000
    Assignee: Intel Corporation
    Inventors: Vishram Prakash Dalvi, Rodney R. Rozman, Christopher John Haid, Jerry Kreifels, Joseph Tsang, Jeff Evertt, Jahanshir J. Javanifard, Jeffrey J. Peterson
  • Patent number: 6073239
    Abstract: A method is disclosed for protecting executable computer programs against infection by a computer virus program. The invented method prevents writing operations that attempt to modify portions of the program, such as the program's entry point or first instructions. A writing operation that attempts to write data to the program is intercepted and analyzed before the operation is allowed to be processed. The method selects significant data and stores the data, in order to retain information indicative of the program prior to any modification thereof. The invented method then determines if the writing operation is attempting to modify the significant data, and if it is determined that the writing operation is attempting to modify the data, an alarm is generated and operation is denied. If it is determined that the writing operation is not attempting to modify the data, the writing operation as allowed to continue.
    Type: Grant
    Filed: September 19, 1997
    Date of Patent: June 6, 2000
    Assignee: In-Defense, Inc.
    Inventor: Eyal Dotan
  • Patent number: 6070254
    Abstract: A high performance file system (HPFS) is validated by checking the directory entries to the extent possible, saving the information required to check F-Nodes and queuing detected errors together with corrective actions. The F-Nodes are then checked in order, minimizing the head motion required to read the F-Nodes and also reducing the I/O time required for the validation process. The detected errors may then be processed, corrective action taken, and the affected DIRBLK written. To reduce the amount of memory required, the directory structure of an HPFS storage device may be processed employing a breadth-first, level-by-level approach. Checking of the directory entries may be further segmented into multiple threads to take advantage of the ability of RAID systems to issue multiple read requests.
    Type: Grant
    Filed: October 17, 1997
    Date of Patent: May 30, 2000
    Assignee: International Business Machines Corporation
    Inventors: Steven L. Pratt, Benedict M. Rafanello
  • Patent number: 6070251
    Abstract: A method and apparatus for high availability and caching data storage devices. According to a preferred embodiment of the invention, there is provided an apparatus. The apparatus comprises a primary controller, a secondary controller having the same address as that of the primary controller, a switching circuit coupled to the primary and secondary controllers, and a control circuit coupled to the switching circuit. According to this preferred embodiment of the invention, in a normal operation, the control circuit sets the switching circuit so that the primary controller receives and responds to input data supplied from a host, and the secondary controller receives the input data. In a fail-over operation in which the primary controller fails, the control circuit sets the switching circuit so that the primary controller is disabled, and the secondary controller receives and responds to the input data supplied from the host. The fail-over is transparent to the host.
    Type: Grant
    Filed: June 26, 1997
    Date of Patent: May 30, 2000
    Assignee: Sun Microsystems, Inc.
    Inventor: Fay Chong
  • Patent number: 6067640
    Abstract: A set of a management-use memory medium in which is written various type of regulatory information (limit I of use of software, limit L of production of the next generation, a number K of generations showing up to what generation backup copies can be produced, software identification information PID, etc.) and a software memory medium in which the software is stored is established and use of the software is allowed under the restrictions of this regulatory information. Further, the software memory medium and the management-use memory medium may be provided in the same memory medium or the two may be constituted as separate memory media. In the case of the latter separate management system, the software is allowed to be used only when the software identification information PID written in the two match. It is therefore possible to suppress the unauthorized use of software without detracting from the spatial convenience of software use.
    Type: Grant
    Filed: March 17, 1998
    Date of Patent: May 23, 2000
    Assignee: Fujitsu Limited
    Inventors: Ryota Akiyama, Naoya Torii
  • Patent number: 6067639
    Abstract: A computer operable method for integrating and automating test procedures within a computer application program. Instantiated test operation objects of an object class defined by the present invention correspond to functions to be tested within the computer application program. The test operation objects are instantiated by calls to functions in a test operation runtime library (DLL). The test operation objects include interface method functions which execute the intended test operation and simulate any required data, file, or memory I/O. Other aspects of the methods of the present invention provide rules which permit decisions as to the applicability of each test operation given the state of the application program or the context of the test operation sequence. The various test operation objects are selected to perform a sequence of test steps. In one mode of operation, the methods of the present invention randomly select among all the instantiated test operation objects.
    Type: Grant
    Filed: November 9, 1995
    Date of Patent: May 23, 2000
    Assignee: Microsoft Corporation
    Inventors: James Perry Rodrigues, Orville Jay Potter, IV
  • Patent number: 6067636
    Abstract: A real time stream server using a disk device data restoration scheme, capable of shortening a restoration time by maximally utilizing the available stream resources, while providing the same service as in a case of normal operation, without setting any limitation on a new stream connection request during the restoration of lost data of a disabled disk device on a spare disk. The operations of the real time stream server is controlled by using normal streams for data transfer and restoration streams for data restoration, where as many stream resources as necessary are allocated to the normal streams first, and then at least a part of remaining stream resources are allocated to the restoration streams.
    Type: Grant
    Filed: September 12, 1996
    Date of Patent: May 23, 2000
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hiroshi Yao, Tatsunori Kanai, Toshiki Kizu, Seiji Maeda
  • Patent number: 6067645
    Abstract: A display apparatus includes a communication device for executing a communication with a host computer via an interface cable. The display apparatus also includes a display having a display screen for displaying image data transferred in synchronism with display timing from the host computer via the interface cable, a connector connectable to the interface cable that communicates with the host computer, and a detector for detecting whether or not the connector is connected to the host computer via the interface cable. A connection/disconnection state of the interface cable is recognized on the basis of the detection result.
    Type: Grant
    Filed: May 30, 1996
    Date of Patent: May 23, 2000
    Assignee: Canon Kabushiki Kaisha
    Inventors: Takashi Yamamoto, Atsushi Mizutome, Akio Yoshida, Hideo Mori, Kazuhiko Murayama, Tomoyuki Ohno
  • Patent number: 6067635
    Abstract: The invention relates to a method and apparatus for maintaining data/parity consistency in a RAID data storage system. The invention utilizes reserved disk storage space in the RAID array to log data necessary to restore data/parity consistency should an interruption event, such as a power failure, corrupt the data stored in a particular redundancy group. In one embodiment, the invention logs new data and new parity information to the reserved disk storage space before the new data and new parity information are written to the appropriate locations in the associated redundancy group. In this way, if an interruption event occurs when either the new data or the new parity information has already been written to the redundancy group but the other has not, the corresponding data and parity information stored in the reserved disk storage space can be used to restore data/parity consistency after the event has ended.
    Type: Grant
    Filed: September 4, 1997
    Date of Patent: May 23, 2000
    Assignee: LSI Logic Corporation
    Inventors: Rodney A. DeKoning, Donald R. Humlicek, Max L. Johnson, Curtis W. Rink
  • Patent number: 6065134
    Abstract: A method provides an on-chip repair technique to fix defective row or I/O memory lines in an ASIC memory array with redundancy row or I/O memory lines. The method employs progressive urgency and dynamic repair schemes to optimize the allotted time for repairing defective row and I/O memory lines. Progressive urgency scheme increases the need to repair relative to the available redundancy row or I/O memory lines over the entire repairing time. Dynamic repair executes a mandatory-row or a mandatory-I/O repair as defective row or I/O memory lines are detected. In addition, a recurrence error reroutes the address location of a redundancy memory line to another address location of another redundancy memory line in the event that such redundancy memory line itself is defective, and thus requires further repair.
    Type: Grant
    Filed: March 30, 1998
    Date of Patent: May 16, 2000
    Assignee: LSI Logic Corporation
    Inventors: Owen S. Bair, Saravana Soundararajan, Adam Kablanian, Thomas P. Anderson, Chuong T. Le
  • Patent number: 6065133
    Abstract: In a method for determining reliability characteristics for a technical installation, a single FMEA table covering all configurations is initially produced for the whole installation. In its lines, i.e. the description of faults and their consequences, the table also has the rate constants, test periods, repair times and consequences of failure, which are dependent on the configuration of the installation. The table explicitly records how the configuration-dependent entries depend on the respective configuration of the installation. In a further step, configuration-specific FMEA tables geared to a specific configuration of the installation can be extracted from this table. Using the configuration-specific FMEA tables, after conversion into Markov models, reliability characteristics can be calculated for the installation in the particular configuration. (FIG.
    Type: Grant
    Filed: March 31, 1998
    Date of Patent: May 16, 2000
    Assignee: ABB Research Ltd.
    Inventor: Silke Draber
  • Patent number: 6065141
    Abstract: An object of the present invention is that, in a semiconductor memory device having both a redundant circuit and a diagnostic circuit, a memory test for detecting positions of defective memory cells in order to replace the defective memory cells with the redundant circuit can be easily carried out by using the diagnostic circuit. A semiconductor memory device of the present invention includes a normal memory portion, a redundant circuit to replace defective memory cells of the normal memory portion by a units of a word line or a bit line, and a self-diagnostic circuit, and further, in order to realize the object, the device includes a defective cell position storage circuit for storing position information of each defective memory cell when the self-diagnostic circuit detects defective memory cells, and an output circuit for converting position information stored in the defective cell position storage circuit into serial data and outputting the position information.
    Type: Grant
    Filed: July 26, 1993
    Date of Patent: May 16, 2000
    Assignee: Fujitsu Limited
    Inventor: Masaya Kitagawa
  • Patent number: 6065136
    Abstract: A system for carrying out remote diagnosis is established between a maker and its users. Each user has a device controlled by its control computer and the maker has a trouble-diagnosing computer capable of diagnosing troubles which occur in its device. Public telecommunication lines including relay stations each capable of receiving and storing electronic mail messages connect these computers. The control computer of each user has a diagnostic data memory for storing diagnostic data which are used for diagnosing troubles occurring in the device and is capable of setting the diagnostic data in a form of electronic mail receivable by the relay stations. The maker's trouble-diagnosing computer is capable of reading out and saving electronic mail messages from the user's control computers stored at an associated one of the relay stations.
    Type: Grant
    Filed: December 5, 1997
    Date of Patent: May 16, 2000
    Assignee: Shimadzu Corporation
    Inventor: Shoji Kuwabara
  • Patent number: 6065118
    Abstract: The present invention reduces the risk of damage to data or programs in an end user computer system programmed to operate in response to an imported data stream containing one or more mobile program components from an external source. The incoming data stream is screened to identify mobile program components of that data stream. Some of the mobile program components are passed to a program execution location isolated from the end user system prior to being executed to operate in a desired manner. The execution location has an interface with the external source of the data stream and an interface with the end user system. The operation of the interface between the execution location and the end user system is programmed so that only data which has been interacted on by the program component within the execution location in a specified and controlled manner can be passed to and from the end user system.
    Type: Grant
    Filed: September 24, 1996
    Date of Patent: May 16, 2000
    Assignee: Citrix Systems, Inc.
    Inventors: John Albert Bull, David John Otway
  • Patent number: 6065138
    Abstract: A computer activity monitoring system is disclosed for monitoring a user's input on a computer having a processor, memory, and input unit. The system functions by first initializing an activity status indicator in the memory. Next, the activity of the operator's input device is measured over a time period to determine an activity rate. The activity rate is then compared to at least one limit selected from the group consisting of a work limit and a rest limit. If the activity rate is greater than the work limit, then the activity status indicator is adjusted according to a first function. If the activity is less than the rest limit, then the activity status indicator is adjusted according to a second function. A warning is indicated if the activity status indicator reaches a predetermined alarm level. Also disclosed is an apparatus for performing this method and a computer readable medium, such a floppy disk, hard drive, CD ROM, or tape, having instructions for performing this method.
    Type: Grant
    Filed: January 7, 1997
    Date of Patent: May 16, 2000
    Assignee: Magnitude LLC
    Inventors: Brian J. Gould, Steven D. Rudnik
  • Patent number: 6061795
    Abstract: The present invention involves a desktop administration system and method which allows a network administrator to remotely create, protect, and manage desktops and control file systems across a network. The invention provides a graphic user interface to construct user desktops, apply restriction options, maintain transaction logs, and password protect any object accessible from the user workstation. The server software operates to lock out any unpermitted users, allowing access to programs or processes presenting appropriate keys or other authentication information. Each workstation includes a personal desktop facility (PDF) and a Daemon which protects the user's desktop. The PDF receives desktop information from the network server and builds a desktop which the user manipulates to invoke local and/or network programs and access local and/or network utilities, providing appropriate keys or other authentication information to access restricted network resources.
    Type: Grant
    Filed: May 12, 1997
    Date of Patent: May 9, 2000
    Assignee: Pinnacle Technology Inc.
    Inventors: Charles E. Dircks, Eric E. Osmann
  • Patent number: 6058493
    Abstract: A system, method, and computer program product for performing an evaluation of a software product wherein a logging module stores in a storage area, such as log file, a description of each loggable test step performed by automated test software. When the automated test is complete or when the software product has filed the automated test, the logging module can write the contents of the log file to a tangible medium so that a user can determine the source of the error or manually reproduce the test steps.
    Type: Grant
    Filed: April 15, 1997
    Date of Patent: May 2, 2000
    Assignee: Sun Microsystems, Inc.
    Inventor: Stephen C. Talley
  • Patent number: 6058497
    Abstract: A testing system evaluates one or more integrated circuit chips using RF communication. The system includes an interrogator unit with a radio communication range, and an IC chip adapted with RF circuitry positioned remotely from the interrogator unit, but within the radio communication range. The interrogator unit transmits a power signal to energize the IC chip during test procedures, and interrogating information for evaluating the operation of the IC chip. Test results are transmitted by the IC chip back to the interrogator unit for examination to determine whether the IC chip has a defect. In this manner, one or more IC chips can be evaluated simultaneously without physically contacting each individual chip.
    Type: Grant
    Filed: November 20, 1992
    Date of Patent: May 2, 2000
    Assignee: Micron Technology, Inc.
    Inventor: Mark E. Tuttle
  • Patent number: 6055664
    Abstract: Where a recording medium recorded on a slave side apparatus is reproduced, it has been made possible to perform on site modification processing identical to that conducted at a master side apparatus, by reproducing, the primary information added with parity symbol for error correction from the recording medium on which the primary information is recorded, correcting the symbol error of primary information reproduced at the reproducing unit using the reproduced parity symbol, producing the flag which indicates the production of an uncorrectable symbol error in one unit of a block of a specified amount of information and thus outputting the modification information corresponding to the primary information and the flag and forming, at the slave side, the parity symbol for correction of error of primary information output at the master side apparatus and recording the primary information with the parity symbol and modification information, on the same recording medium.
    Type: Grant
    Filed: September 30, 1994
    Date of Patent: April 25, 2000
    Assignee: Canon Kabushiki Kaisha
    Inventors: Yoshiki Ishii, Akihiro Shikakura, Tetsuya Shimizu
  • Patent number: 6055638
    Abstract: Process and device for secured authentication of the transmission of data between two terminals includes a secured authentication process for the communication between a user's station and a server station, through a communication network, the user's station bring the content of an authentication device depending on information coming from a server station, in which a link is established between the user's station and the server station, a server code is chosen at random at the level of the server station, representative data of the server code are transmitted in a first server-to-user direction, thanks to those data, a corresponding user's code is recognized in the content of the authentication device, the recognized user's code is transmitted in a second user-to-server direction, the user's code is compared with the server code, and the authentication is validated if the user's code is identical to the server code.
    Type: Grant
    Filed: August 15, 1997
    Date of Patent: April 25, 2000
    Inventors: Thoniel Pascal, Cottreau Thierry