Abstract: A non-volatile memory device based on an array of floating gate memory cells includes read, erase, program and verify control logic for the array. A status register is coupled with the control logic and stores statistics determined during verify operations concerning at least one of the erase and program operations. For instance, the control logic may include erase verify resources and program verify resources, and the statistics will indicate a number of memory cells which fail erase or program verify. Alternatively, the statistics may indicate whether a threshold number of sequential bytes in the memory fail program verify for a program or erase operation involving a page or sector of data. In addition, defective addresses can be stored. With the status register, the number of program and erase retries for the device can be significantly reduced, allowing application of the device to real time storage systems. Many real time storage problems are fault tolerant.

Abstract: A test mode matrix circuit in an integrated circuit switches signal lines internal to the integrated circuit in a manner that allows an embedded microprocessor within the integrated circuit to be fully functionally tested using standard test vectors applied to the integrated circuit, and which allows for debugging the code written for an embedded microprocessor core by connecting an in-circuit emulator (ICE) to the integrated circuit. The test mode matrix circuit operates in a number of mutually exclusive modes, each of which is suitably selected via control signal inputs to the test mode matrix. The test mode matrix circuit couples signals from the embedded microprocessor to the application-specific logic without passing through off-chip drivers/receivers. Multiple microprocessors and corresponding test mode matrices may also be implemented on the same integrated circuit.

Abstract: A shift register is used to latch the bus-driver-enable signal for each potential bus driver during each system clock cycle. The shift register clock will freeze upon receipt of a "check stop" signal. Once frozen, the shift register can be scanned for fault isolation analysis.

Abstract: A method is disclosed for providing error correction for an array of disks using non-volatile random access memory (NV-RAM). Non-volatile RAM is used to increase the speed of RAID recovery from a disk error(s). This is accomplished by keeping a list of all disk blocks for which the parity is possibly inconsistent. Such a list of disk blocks is much smaller than the total number of parity blocks in the RAID subsystem. The total number of parity blocks in the RAID subsystem is typically in the range of hundreds of thousands of parity blocks. Knowledge of the number of parity blocks that are possibly inconsistent makes it possible to fix only those few blocks, identified in the list, in a significantly smaller amount of time than is possible in the prior art. The technique for safely writing to a RAID array with a broken disk is complicated. In this technique, data that can become corrupted is copied into NV-RAM before the potentially corrupting operation is performed.

Abstract: A system and method for the automated maintenance of a computer system. A scheduler periodically activates sensors. When activated, the sensors gather information about various aspects of the computer system. The sensors store this information in a knowledge database. The knowledge database also contains cases, questions, and actions. The cases describe potential computer problems and solutions. The questions are used to diagnose the problems while the actions describe steps that can be taken to solve the diagnosed problems. If the information gathered by the sensors indicates a problem with the computer system, then the sensors activate an artificial intelligence engine. The engine uses the information in the knowledge database to evaluate certain cases. If information necessary to evaluate a case is not in the knowledge database, then the engine activates a sensor to gather the information. As the cases are evaluated, the confidence levels of certain other cases, questions, and actions increase.

Abstract: Channel data obtained from a reproduced signal is input to a demodulation ROM as an address and demodulated. In the demodulated channel data, the data whose data pattern is not consistent with a 2-7 modulation method is recognized as an error data. When a resync code, given in the channel data at every 15 bytes is not detected within a predetermined time period, a resync code undetected signal is generated. The demodulated data is arranged in a matrix, and the position of the error data in the matrix and the resync code undetected generation position are specified. An error correction circuit carries out the error correction (erasure correction) by using these positions and an error correction code relating to one direction of a row or a column of the matrix.

Abstract: A plurality of parity bits is generated for serial transmission of a word of data bits, and the plurality of parity bits is modified before transmission to encode a sideband signal. The word of data bits and the plurality of modified parity bits are serially transmitted. In another embodiment, a serially-transmitted code word comprising a word of data bits and a plurality of parity bits is received, wherein the parity bits have been generated by an encoder and transmitted with the data bits. It is determined whether the parity bits were modified by the encoder to encode a sideband signal, and at least one of error detection and error correction is performed using the parity bits.

Abstract: A computer software system (10) is provided. The computer software system (10) includes a compiler (12) operable to receive a worksheet definition (20) and to access a plurality of model interface functions (16). The worksheet definition (20) is named and parameterized and comprises a plurality of cell definitions (24) each defining a model-independent expression (26). The compiler (12) is further operable to generate a worksheet template (32) comprising a plurality of cell templates (36) each defining a model-dependent expression (38). An evaluator (40) is operable to receive the worksheet template (32) and a parameter expression. The evaluator (40) is further operable to access the plurality of model interface functions (16) and a user model (60). The evaluator (40) is operable to evaluate the model-dependent expressions (38) in the worksheet template (32) and is operable to generate a worksheet instance (48) containing a plurality of cell instances (52) defining model-specific values (54).

Abstract: A system and method for preventing damage to media files within a digital camera comprises a power manager for detecting power failures, an interrupt handler for responsively incrementing a counter device and a removable memory driver for performing memory access operations, evaluating the counter device to determine whether a power failure has occurred during the memory access operation and for repeating the memory access operation whenever a power failure has occurred during the memory access operation.

Abstract: A memory fault correction system enables data to be written to and read from memory devices having a relatively large number of defective storage locations. For each address of the memory device, there are a plurality of storage locations corresponding in number to the number of bits of data to be stored, a plurality of substitute storage locations in which data is stored instead of being stored at defective memory locations, and a plurality of identifying locations in which data is stored identifying the defective memory locations at each address. In a write operation to an address, the identifying locations at the address are read to identify the defective memory locations at that address. The data that would otherwise be written to the defective memory locations is then instead written to the substitute memory locations. The remaining data is written to the corresponding locations at the address.

Abstract: An automated method is provided, in concert with applications programs, to recover data potentially lost in a database unavailable/crash or system failure, by use of an update transaction log that maintains current copies of any update to a system data base before any application program actually physically updates the system data base. The update transaction log is a temporary stored record of application transactions and the relevant data to be stored in the data base. The transaction log is a part of the application program and is operative whenever the application program is generating data which must be added to a relevant data base. If the database is unavailable, the external system update request can still be processed for the lagging update.

Abstract: A system and method for restoring communications in a network having multiple span failures. After a failure is detected, a sender node in each of the plurality of sender-chooser pairs sends a failed status message to the other nodes in the network. The failed status message identifies a restoration priority of the particular sender-chooser pair. Upon receipt, other nodes in the network suspend processing of lower priority restoration efforts and queue lower priority messages if they are preempted by higher priority messages. Lower priority restoration efforts resume upon receipt of a finished status message from the sender node of the higher priority sender-chooser pair.

Abstract: A RAID array includes redundant storage devices. Data is distributed across the storage devices, and organized as slivers of RAID protected data blocks. This redundancy provides for the reconstruction of valid data when data at a particular data block of a sliver is found to be inconsistent. However, when more than one data block of a sliver is found to have inconsistent data, reconstruction of the inconsistent data blocks may not be possible. Nonetheless, data consistency can still be restored to that sliver. Consistency is restored to such a sliver by replacing any inconsistent data in a data block with predetermined data and reconstructing the parity data block using the predetermined data. Other data in the RAID array keeps track of those data blocks with the predetermined data to indicate that such blocks do not contain valid data.

Abstract: A memory fault correction system enables data to be written to and read from memory devices having a relatively large number of defective storage locations. For each address of the memory device, there are a plurality of storage locations corresponding in number to the number of bits of data to be stored, a plurality of substitute storage locations in which data is stored instead of being stored at defective memory locations, and a plurality of identifying locations in which data is stored identifying the defective memory locations at each address. In a write operation to an address, the identifying locations at the address are read to identify the defective memory locations at that address. The data that would otherwise be written to the defective memory locations is then instead written to the substitute memory locations. The remaining data is written to the corresponding locations at the address.

Abstract: In the case of processor or installations, or both, which are monitored by sequence control from a PLC program which is produced as a contact plan (KOP), as a function plan (FUP) or as an instruction list (AWL), the AWL code of the PLC program is analyzed by machine and is prepared in the form of a knowledge base, according to the invention, in order to prepare for diagnosis. Step chain analysis and/or a transition analysis are/is carried out in order to prepare the knowledge base.

Abstract: A fault tolerant circuit having improved error correction and detection properties takes advantage of two distinct forms of information redundancy: modular redundancy and parity check bit redundancy, in a cooperative fashion. In particular, it is shown that simple majority voting logic circuits, when employed in the subject environment, provide an easily realized mechanism for error correction and error detection. This results in an extremely fault tolerant information system.

Abstract: A network-based telecommunications system and method that restricts the dial-in access to a resource of a subscriber to only a communication from an authorized user of the resource. A switch receives a communication directed to a subscriber from a calling party. Prior to connecting the communication to the terminating equipment associated with the subscriber, the switch requests processing information. An authentication unit determines whether the calling party is an authorized user by checking whether a passcode provided by the calling party corresponds to a passcode being held by the authentication unit. If the passcode corresponds, then the authentication unit identifies the calling party as an authorized user, and the communication then may be connected to the terminating equipment of the subscriber. If the passcode fails to correspond, then the authentication unit fails to identify the calling party as an authorized user. The communication is not connected to the terminating equipment of the subscriber.

Abstract: A program is made secure relative to a CPU by storing in a first memory zone a series of predetermined-address functions that are directly executable by the CPU, by write protecting said first memory zone, and by storing the program in a second memory zone in the form of a series of instructions that are executable within the second memory zone or that activate functions contained in the first memory zone.