Abstract: Upon sequentially transmitting plural data frames to one destination address, each communication apparatus inverts “1” or “0” of a switch flag to add a new switch flag to a source address and a destination address, in a flag setting section, and the source address and the destination address added with the new flag are transmitted as a monitor data. Each communication apparatus receives all data frames on a network, and the monitor data of the data frames received in a preceding time and in a present time are compared with each other, in a malfunction detecting section. By the inversion control of the switch flag, the monitor data of the data frames received in the preceding time and in the present time cannot be equal to each other. Therefore, a malfunction specifying section detects a comparison result output indicating coincidence between the monitor data, thereby to detect occurrence of a trouble.

Abstract: A method and apparatus to determine user identity and limit access to a communications network. A first message containing user identity information is received from a client computer in accordance with a first protocol. A first network address is determined from the first message. A second message containing an information request is also received from the client in accordance with a second protocol, and a second network address is determined from the second message. The requesting user identity is then determined based on the first network address, the user identity information and the second network address. Based on the requesting user identity, it can be decided whether to grant the information request. If access is granted, the requested information is retrieved using the communications network.

Abstract: A network of microcontrollers for monitoring and diagnosing the environmental conditions of a computer is disclosed. The network of microcontrollers provides a management system by which computer users can accurately gauge the health of their computer. The network of microcontrollers provides users the ability to detect system fan speeds, internal temperatures and voltage levels. The invention is designed to not only be resilient to faults, but also allows for the system maintenance, modification, and growth—without downtime. Additionally, the present invention allows users to replace failed components, and add new functionality, such as new network interfaces, disk interface cards and storage, without impacting existing users. One of the primary roles of the present invention is to manage the environment without outside involvement. This self-management allows the system to continue to operate even though components have failed.

Abstract: A method and apparatus for fast and reliable fencing of resources such as shared disks on a networked system. For each new configuration of nodes and resources on the system, a membership program module generates a new membership list and, based upon that, a new epoch number uniquely identifying the membership correlated with the time that it exists. A control key based upon the epoch number is generated, and is stored at each resource controller and node on the system. If a node is identified as failed, it is removed from the membership list, and a new epoch number and control key are generated. When a node sends an access request to a resource, the resource controller compares its locally stored control key with the control key stored at the node (which is transmitted with the access request). The access request is executed only if the two keys match.

Abstract: A system for providing uninterrupted communication over a network link includes a multi-port switch that is connected to a first network portion and a second network portion that are communicating with one another. The multi-port switch is also connected to a separate server unit, such as a firewall computer. The switch is configured to direct communication signals flowing between the first network portion and the second network portion through the separate server unit for processing during normal operation. When the separate server unit fails, however, the switch is reconfigured so that communications bypass the separate server unit. In a preferred embodiment, a Ethernet switch having virtual local area network (VLAN) capability is used.

Abstract: A computer system includes a system bus, peripheral devices, bus control logic having bus control lines for bus master operation, and an allocation control circuit. The allocation control circuit is connected to at least one of the bus control lines and at least two of the peripheral devices. The connected bus control line is coupled to one of the connected peripheral devices by the allocation unit so that the one connected peripheral device can operate as a bus master on the system bus. In a preferred embodiment, the allocation control circuit includes switches that are controlled by the system software. Also provided is a method of allocating bus master control lines to peripheral devices. According to the method, the bus master control lines and the peripheral devices are connected to an allocation unit.

Abstract: An electronic document management system comprising access right list assignment unit for assigning an access right list setting an authorization system name, user name, and access right to an electronic document, access authorization unit for inquiring of an authorization system specified by a user who the user is when the electronic document is opened, and access right recognition means for recognizing the access right assigned to the authorized user from the access right list. To open an electronic document, the user is authorized in the authorization system specified by the user and the access right assigned to the authorized user is recognized from the access right list, then display and edit unit opens the electronic document in accordance with the recognized access right, whereby if the electronic documents confidential in each system are moved to another system, the access rights are also moved with the electronic documents, so that security of the electronic documents can be provided.

Abstract: A standard physical medium 1320 as loaded into library unit 1080 even in the absence of any load request from a host computer 1020 is regarded as a spare physical medium 1330 for use when the standard physical medium 1320 is under malfunction, and such medium is put in a spare media storage space 1340 while eliminating issuance of any notice to the host computer 1020. Whereby, in a computer system with redundancy configuration, it becomes possible to prevent the host computer from making use of any spare physical media.

Abstract: A computer system used in monitoring another computer system provides both textual resolution information describing a likely solution for a problem encountered in the monitored computer system as well as component information that relates to the particular problem. The component information includes the various hardware, software and operating conditions found in the monitored computer system. The monitoring computer system determines if a condition of a predetermined severity exists in the monitored computer system according to diagnostic information provided from the monitored computer system. The diagnostic information is represented in the monitoring computer system as a hierarchical representation of the monitored computer system. The hierarchical representation provides present state information indicating the state of hardware and software components and operating conditions of the monitored computer system.

Abstract: A secure interface between a private network and a public network are disclosed. The interface includes a collection of routing devices, telecommunications devices, packet-filtering devices, applications-filtering devices, monitoring and maintenance devices organized to enforce a wide variety of desired customer security policies. The apparatus allows a central service provider to install and maintain a collection of similar apparatus and support a number of customers with widely varying security policies and allows a rapid change in the security policy of a given customer, without affecting the security of other customers, and without requiring the customer to understand or modify the underlying apparatus.

Abstract: A test-facilitating circuit selectively carries out tests for self-testing and for fault diagnosis and failure analysis. In a test for fault diagnosis or failure analysis, necessary test data are supplied from outside the circuit and microprograms for self-testing are used. When carrying out a test for fault diagnosis or failure analysis, a test data generating circuit for self-testing is inhibited from outputting test data to an internal bus and test data are taken in by the internal bus from external input terminals in accordance with a microinstruction.

Abstract: In a semiconductor device including a high power supply line, a low power supply line, and a CMIS gate circuit having a high voltage side terminal, a low voltage side terminal and an output terminal, a first switching element is connected between the high voltage side terminal and the high power supply line, a second switching element is connected to the output terminal and the high power supply line, a third switching element is connected between the low voltage side terminal and the low power supply line, and a fourth switching element is connected to the output terminal and the low power supply line.

Abstract: An electronic module having at least a microprocessor and co-processor on a single integrated circuit. The electronic module can be contained in a small housing. The electronic module provides secure bidirectional data communication via a data bus. The electronic module may include an integrated circuit comprising a microprocessor, and a co-processor adapted to handle 1,024-bit modulo mathematics primarily aimed at RSA calculations. The electronic module is preferably contained in a small token sized metallic container and will preferably communicate via a single wire data bus which uses a one-wire protocol.

Abstract: Disclosed are a system and method for providing fault isolation in a computer system including a central processing unit (“CPU”) capable of issuing a signal to a memory to retrieve a requested instruction from the memory when the CPU is booted. The disclosed invention comprises an interception and substitution circuit, coupled to the CPU, capable of intercepting the signal and providing an alternative diagnostics instruction to the CPU in lieu of the requested instruction, the alternative diagnostics instruction providing an indication of proper functioning of the computer system when executed by the CPU. The circuit allows a user to determine whether the CPU and components proximate the CPU are functioning, even when a fault renders conventional, embedded power-on self-test routines non-functional.

Abstract: A method for moderating forums with anonymous but traceable contributions, comprising the steps of: establishing and conducting a moderated forum; receiving from any anonymous contributor an anonymous message and data identifying the contributor's actual user name and an anonymous designation; displaying the data identifying the actual user name and the anonymous designation only to at least one of a moderator and an administrator of the forum, the moderator having an opportunity to authorize or refuse publication of the anonymous message in accordance with rules of the forum and the at least one of the moderator and the administrator having an opportunity to attribute authorship of the anonymous message to the user for further reference; and, upon authorization of publication, publishing the anonymous message to the forum anonymously as to all other contributors.

Abstract: A circuit for diagnosing and debugging a processor for executing a stream of instructions that includes a set of debug registers for identifying an instruction or data address breakpoint; a processor for generating a debug exception in response to an instruction or data address in the stream of instructions matching the instruction or data breakpoint stored in the set of debug registers and a debug configuration register for enabling transfer of program control to one of a plurality of destinations in response to the debug exception. The debug configuration registers may designate system management mode, JTAG routine or a software debug interrupt handler as the destination.

Abstract: The present invention comprises a smart debug interface circuit for the diagnostic testing and debugging of a software application for a programmable digital processor system. The smart debug interface circuit of the present invention includes an instruction register for coupling to an instruction bus of a programmable digital processor. The instruction register is adapted to drive instructions onto the instruction bus. The instruction register couples to the instruction bus in a parallel manner. The smart debug interface circuit of the present invention includes a data register for coupling to a data bus of the programmable digital processor. The data register is adapted to read data from the data bus and couples to the data bus in a parallel manner. The instruction register and data register are each coupled to an interface port. The interface port couples the smart debug interface circuit to a host computer system.

Abstract: A power system fault handling mechanism for portable electronic devices having multiple power supplies. A safety-net circuit is triggered when a power fault condition is detected. The safety-net circuit is a diode-based bridging circuit which couples all available power supplies to the power load, yet avoids feeding power back from any of the supplies to one another. This ensures that the load continues to receive power after a fault condition occurs without interruption. A microcontroller may then implement a routine to switch to a working power supply so that the device may resume normal operation. The power system fault detection mechanism therefor allows for the switching between system power supplies without disrupting a running process.

Abstract: A central processing unit (CPU) repeatedly interrupts execution of software to save the CPU state, i.e. contents of various storage elements internal to the CPU, until an error occurs during the execution. On occurrence of the error, the CPU once again saves state and only then passes control to a handler in the software for handling the error. The state saving steps can be implemented in a computer process by use of a timer interrupt or by use of system management, or ICE breakpoint instructions that are included in the x86 instruction set. Errors can be debugged off-line in a development system, for example, by use of an in-circuit emulator to load the saved CPU states sequentially into the development system, thereby to recreate the error condition. Errors can also be debugged proactively, even before the error occurs, by use of a number of known-to-be-erroneous instructions and corresponding fix instructions.

Abstract: In an arrangement for locating faults in software, a history file is created during running of the software, which file contains values for variables in the software which can then be reviewed in the event of system failure. Review can be carried out in a forwards, backwards or search mode, in the manner of conventional video tape controls by a video type interface between a debugger and the history file created during running of the software.