Abstract: A semiconductor package comprises a lead frame, a chip, and a molding encapsulation. The lead frame comprises one or more die paddles comprising a first die paddle. The first die paddle comprises one or more through holes, one or more protrusions with grooves on top surfaces of the one or more protrusions, or one or more squeezed extensions. Each of the one or more through holes is filled with a respective portion of the molding encapsulation. Each of the one or more through holes may be of a rectangular shape, a rectangular shape with four filleted corners, a circular shape, or an oval shape. Each of the grooves is filled with a respective portion of the molding encapsulation. A respective side wall of each of the one or more squeezed extensions is of a swallowtail shape. The swallowtail shape directly contacts the molding encapsulation.

Abstract: A method of forming a chip package is provided. The method may include: arranging an elastic thermal interface material over a semiconductor chip, wherein the elastic thermal interface material may be configured to transfer heat from the chip to an outside; arranging a mold around the thermal interface material and at least partially around the semiconductor chip, thereby compressing the elastic thermal interface material with the mold; and filling the mold with a packaging material.

Abstract: A silicon carbide epitaxial layer includes a first silicon carbide layer, a second silicon carbide layer, a third silicon carbide layer, and a fourth silicon carbide layer. A nitrogen concentration of the second silicon carbide layer is increased from the first silicon carbide layer toward the third silicon carbide layer. A value obtained by dividing, by a thickness of the second silicon carbide layer, a value obtained by subtracting a nitrogen concentration of the first silicon carbide layer from a nitrogen concentration of the third silicon carbide layer is less than or equal to 6×1023 cm?4. Assuming that the nitrogen concentration of the third silicon carbide layer is N cm?3 and a thickness of the third silicon carbide layer is X ?m, X and N satisfy a Formula 1.

Abstract: The invention relates to a lead frame assembly comprising a plurality of regularly arranged lead frames, each of which is suitable for electrically contacting components, comprises at least two lead frame elements distanced laterally by a recess and which are provided as electrical connections of different polarity, and has at least one anchoring element, which is suitable for anchoring a housing body of the component, the lead frame elements being thinned, flat regions of the lead frame, and the at least one anchoring element protrudes from a plane of the lead frame elements in the form of a pillar, and a plurality of connection elements, which in each case connects two lead frame elements of adjacent lead frames to one another, the two connected lead frame elements being provided as terminals of different polarity.

Abstract: In a described example, an integrated circuit (IC) package includes an IC die disposed on a die attach pad; a plurality of leads electrically connected to terminals on the IC die, the leads including a base metal; and molding compound material encapsulating portions of the IC die, the die attach pads, and the plurality of leads; the plurality of leads having a solder joint reinforcement tab. The solder joint reinforcement tabs include a first side, a second side opposite to the first side, a third side, a fourth side opposite to and in parallel to the third side, a fifth side forming an end portion of the solder joint reinforcement tab, the solder joint reinforcement tabs including a solderable metal layer on the second, third and fourth sides and on portions of the fifth side.

Abstract: A package mold according to some embodiments includes a first mold body and a second mold body, a mold cavity in the first mold body, a gate in a first side of the mold cavity for supplying liquid mold compound into the mold cavity, a longitudinal vent for releasing gas from the mold cavity in a second side of the mold cavity opposite the first side of the mold cavity, and a transverse vent for releasing gas from the mold cavity in a third side of the mold cavity that extends between the first and second sides of the mold cavity. Methods of packaging an electronic device using the package mold and resulting packaged devices are also disclosed.

Abstract: A semiconductor package structure and a method of manufacturing a semiconductor package structure are provided. The semiconductor package structure includes a first electronic device and a second electronic device. The first electronic device has an active surface and a lateral surface angled with the active surface, and the lateral surface includes a first portion and a second portion that is non-coplanar with the first portion. The second electronic device is disposed on the active surface of the first electronic device.

Abstract: A package and method of manufacturing a package is disclosed. In one example, a package which comprises a first transistor chip having a first source pad and a second transistor chip having a second source pad and being stacked with the first transistor chip at an interface area. The first source pad and the second source pad are coupled at the interface area.

Abstract: Embodiments of the present disclosure are directed to a leadframe package with recesses formed in outer surface of the leads. The recesses are filled with a filler material, such as solder. The filler material in the recesses provides a wetable surface for filler material, such as solder, to adhere to during mounting of the package to another device, such as a printed circuit board (PCB). This enables strong solder joints between the leads of the package and the PCB. It also enables improved visual inspection of the solder joints after the package has been mounted.

Abstract: The present disclosure provides a package structure and a method for forming a package structure. The package structure includes a first die having a front surface and a back surface opposite to the front surface; and a thermal management structure over the back surface. The thermal management structure includes a first copper-phosphorous alloy layer thermally coupled to the back surface of the first die.

Abstract: Performance of a semiconductor device is improved. In one embodiment, for example, deposition time is increased from 4.6 sec to 6.9 sec. In other words, in one embodiment, thickness of a tantalum nitride film is increased by increasing the deposition time. Specifically, in one embodiment, deposition time is increased such that a tantalum nitride film provided on the bottom of a connection hole to be coupled to a wide interconnection has a thickness within a range from 5 to 10 nm.

Abstract: A reliable semiconductor module and a reliable power conversion device using the semiconductor module are obtained. A semiconductor module includes a heat dissipation member, a semiconductor device, and a thermally conductive insulating resin sheet. The thermally conductive insulating resin sheet connects the heat dissipation member and the semiconductor device. The semiconductor device includes a semiconductor element and a metal wiring member. The metal wiring member is electrically connected to the semiconductor element. The metal wiring member includes a terminal portion protruding outside the semiconductor device. In a surface portion of the semiconductor device, a concave portion is formed outward of a partial region to which the thermally conductive insulating resin sheet is connected. The concave portion is located in a region closer to the heat dissipation member than the terminal portion.

Abstract: A lead frame includes a first area, situated on a first surface of the lead frame, for mounting a semiconductor chip, and a second area, situated on the first surface of the lead frame, around the first area, wherein the second area includes a roughened area and a less-rough area situated between the roughened area and the first area, the less-rough area having a higher flatness than the roughened area.

Abstract: A semiconductor device includes a substrate and a semiconductor die including an active surface with bond pads, an opposite inactive surface, and stepped side surfaces extending between the active surface and the inactive surface. The stepped side surfaces include a first planar surface extending from the inactive surface towards the active surface, a second planar surface extending from the active surface towards the inactive surface, and a side surface offset between the first planar surface and the second planar surface. The semiconductor device further includes an adhesive layer covering at least a portion of a surface area of the second surface and attaching the semiconductor die to the substrate.

Abstract: A semiconductor device includes a semiconductor chip, an insulated circuit board including a metal plate, an insulating plate and a circuit pattern, each of which has a rectangular shape, and a spacer part disposed on the periphery of a rear surface of the metal plate including at least one of the four corners thereof. The spacer part protrudes from a rear surface of the metal plate in the thickness direction away from a front surface of the insulated circuit board.

Abstract: A semiconductor package includes a base substrate that includes a first surface and a second surface that face each other, a plurality of first metal line patterns disposed on the first surface, a plurality of second metal line patterns disposed on the second surface, a plurality of vias that penetrate the base substrate and connect the first metal line patterns to the second metal line patterns, a semiconductor chip disposed on the first surface, and a molding member that covers the first surface and the semiconductor chip. The base substrate includes at least one recess at a corner of the base substrate. The recess extends from the first surface toward the second surface. The molding member includes a protrusion that fills the recess.

Abstract: A multichip package and a method for manufacturing the same are provided. A multichip package includes: a plurality of semiconductor chips each mounted on corresponding lead frame pads; lead frames connected to the semiconductor chips by a bonding wire; and fixed frames integrally formed with at least one of the lead frame pads and configured to support the lead frame pads on a package-forming substrate.

Abstract: In one example, a packaged electronic device includes a molded substrate. The molded substrate includes a conductive structure having an edge lead with an edge lead outward side and an edge lead inward side opposite to the edge lead outward side, and an inner lead having an inner lead outward side and an inner lead inward side opposite to the inner lead outward side. The molded substrate includes a substrate encapsulant covering a lower portion of the edge lead inward side, a lower portion of the inner lead inward side, and a lower portion of the inner lead outward side. An upper portion of the edge lead outward side and an upper portion of the inner lead outward side are exposed from the substrate encapsulant. An electronic component is connected to the edge lead and the inner lead. A body encapsulant covers the electronic component and portions of the conductive structure.

Abstract: An electronic device structure and a method for making an electronic device. As non-limiting examples, various aspects of this disclosure provide a method of manufacturing an electronic device that comprises the utilization of a carrier assisted substrate, and an electronic device manufactured thereby.

Abstract: A manufacturing method of a semiconductor package is provided. The method includes: providing an initial rigid-flexible substrate, wherein the initial rigid-flexible substrate includes rigid structures and a flexible core laterally penetrating through the rigid structures, and further includes a supporting frame connected to the rigid structures; bonding a package structure onto the initial rigid-flexible substrate, wherein the package structure includes semiconductor dies and an encapsulant laterally surrounding the semiconductor dies; and removing the supporting frame.