Patents Examined by Dilinh P. Nguyen
  • Patent number: 10541207
    Abstract: At least one opening having a biconvex shape is formed into a dielectric material layer. A void-free metallization region (interconnect metallic region and/or metallic contact region) is provided to each of the openings. The void-free metallization region has the biconvex shape and exhibits a low wire resistance.
    Type: Grant
    Filed: December 28, 2018
    Date of Patent: January 21, 2020
    Assignee: International Business Machines Corporation
    Inventors: Praneet Adusumilli, Alexander Reznicek, Oscar van der Straten
  • Patent number: 10541354
    Abstract: A light source device includes an electronic component and a substrate. The electronic component includes first and second electrodes exposed at a lower surface. The first electrode includes first and second parts separated from each other by a separation region on the lower surface of the electronic component. The substrate includes a basal member and a first and second wiring layers disposed on an upper surface of the basal member. The electronic component is mounted to the substrate so that upper surfaces of the first and second wiring layers respectively face the first and second electrodes. The substrate includes a first region at a position overlapping the separation region as seen in a top view. Solder wettability of the substrate in the first region is lower than solder wettability of the substrate in at least regions of the first wiring layer facing the first and second parts of the first electrode.
    Type: Grant
    Filed: April 20, 2018
    Date of Patent: January 21, 2020
    Assignee: NICHIA CORPORATION
    Inventors: Takeshi Aki, Ryosuke Wakaki
  • Patent number: 10535587
    Abstract: Packaged semiconductor device having a frame, of conductive material; a body of semiconductor material, fixed to the frame through a first adhesive layer; a heat-sink element, fixed to the body through a second adhesive layer; and a packaging mass surrounding the body and, at least partially, the frame and the heat-sink element. The heat-sink element is formed by a heat-sink die facing, and coplanar to, a main face of the device and by a spacer structure, which includes a pair of pedestals projecting from the perimeter of the heat-sink die towards the body and rest on the body.
    Type: Grant
    Filed: December 7, 2015
    Date of Patent: January 14, 2020
    Assignee: STMICROELECTRONICS S.R.L.
    Inventors: Concetto Privitera, Maurizio Maria Ferrara, Fabio Vito Coppone
  • Patent number: 10522664
    Abstract: An electronic device includes a semiconductor layer, a tunneling layer formed of a material including a two-dimensional (2D) material so as to directly contact a certain region of the semiconductor layer, and a metal layer formed on the tunneling layer.
    Type: Grant
    Filed: February 26, 2018
    Date of Patent: December 31, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Kyungeun Byun, Jisoo Kyoung, Seongjun Park, Hyeonjin Shin, Hyunjae Song, Jaeho Lee
  • Patent number: 10510841
    Abstract: A silicon carbide semiconductor device includes: n type regions formed on a surface of the n? type epitaxial layer; p type body regions formed at positions deeper than the n type regions; p? type channel regions each reaching the p type body region; and n++ type source regions formed toward the p type body region from the front surface side of the epitaxial layer, and the p? type channel regions and the n++ type source regions are formed at a planar position where the n type region remains between the p? type channel region and the n++ type source region, and out of boundary surfaces which are formed between the p? type channel region and the n type regions, the boundary surface on an outer peripheral side is positioned inside an outer peripheral surface 116a of the p type body region as viewed in a plan view.
    Type: Grant
    Filed: April 18, 2019
    Date of Patent: December 17, 2019
    Assignee: SHINDENGEN ELECTRIC MANUFACTURING CO., LTD.
    Inventors: Shunichi Nakamura, Akihiko Sugai, Tetsuto Inoue
  • Patent number: 10504867
    Abstract: A semiconductor device has a bonding pad and a wiring layer formed on an insulating film. The wiring layer is spaced from the bonding pad by a gap. A passivation film covers the bonding pad and the wiring layer and fills the gap. The gap has a width equal to or larger than the thickness of the passivation film, and equal to or smaller than twice a side wall thickness of the passivation film covering a side wall of the wiring layer. The semiconductor device has a high resistance to stress during bonding.
    Type: Grant
    Filed: June 27, 2016
    Date of Patent: December 10, 2019
    Assignee: ABLIC Inc.
    Inventor: Koichi Shimazaki
  • Patent number: 10490539
    Abstract: A semiconductor device includes a first package component and a second package component. The first package component has a first die formed on a first substrate. A second package component has a second die formed on a second substrate. A thermal isolation material is attached on the first die, wherein the thermal isolation material thermally insulates the second die from the first die, and the thermal isolation material has a thermal conductivity of from about 0.024 W/mK to about 0.2 W/mK. A first set of conductive elements couples the first package component to the second package component.
    Type: Grant
    Filed: August 4, 2016
    Date of Patent: November 26, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Meng-Tse Chen, Kuei-Wei Huang, Tsai-Tsung Tsai, Ai-Tee Ang, Ming-Da Cheng, Chung-Shi Liu
  • Patent number: 10461026
    Abstract: Techniques for improving reliability in Cu interconnects using Cu intermetallics are provided. In one aspect, a method of forming a Cu interconnect in a dielectric over a Cu line includes the steps of: forming at least one via in the dielectric over the Cu line; depositing a metal layer onto the dielectric and lining the via such that the metal layer is in contact with the Cu line at the bottom of the via, wherein the metal layer comprises at least one metal that can react with Cu to form a Cu intermetallic; annealing the metal layer and the Cu line under conditions sufficient to form a Cu intermetallic barrier at the bottom of the via; and plating Cu into the via to form the Cu interconnect, wherein the Cu interconnect is separated from the Cu line by the Cu intermetallic barrier. A device structure is also provided.
    Type: Grant
    Filed: June 30, 2016
    Date of Patent: October 29, 2019
    Assignee: International Business Machines Corporation
    Inventors: Chao-Kun Hu, Christian Lavoie, Stephen M. Rossnagel, Thomas M. Shaw
  • Patent number: 10461020
    Abstract: A QFP has a die pad on which a semiconductor chip is mounted, a plurality of inner parts disposed around the die pad, a plurality of outer parts respectively connected with the plurality of inner parts, a plurality of wires electrically connect the bonding pads of the semiconductor chip and the plurality of inner parts, and a sealing body that seals the semiconductor chip. Moreover, the thickness of the semiconductor chip is larger than a thickness from a lower surface of the die pad to a lower surface of the sealing body, and a distance from the lower surface of the sealing body to a tip portion of each of the plurality of outer parts is larger than a thickness of the sealing body from a main surface of the semiconductor chip to an upper surface of the sealing body.
    Type: Grant
    Filed: June 26, 2018
    Date of Patent: October 29, 2019
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Noriyuki Takahashi
  • Patent number: 10461030
    Abstract: Step shape pad structure and wiring structure in vertical type semiconductor device are include a first conductive line having a first line shape and including first pad regions at an upper surface of an edge portion, and a second conductive line having s second line shape and being spaced apart from the first conductive line and provided on the first conductive line. An end portion of the first conductive line is extended to a first position. Second pad regions are included on an upper surface of an edge portion of the second conductive line. An end portion of the second conductive line is extended to the first position. The second conductive line includes a dent portion at a facing portion to the first pad regions in a vertical direction to expose the first pad regions. The pad structure may be used in a vertical type nonvolatile memory device.
    Type: Grant
    Filed: October 21, 2016
    Date of Patent: October 29, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sung-Min Hwang, Young-Ho Lee, Seong-Soon Cho, Woon-Kyung Lee
  • Patent number: 10438887
    Abstract: The present disclosure provides a semiconductor chip having a non-through plug contour (buried alignment mark) for stacking alignment and a multi-chip semiconductor device employing thereof, and to a method for manufacturing same. In some embodiments, the semiconductor chip includes a semiconductor substrate having a first side and a second side, a conductive through plug extending through the semiconductor substrate from the first side to the second side, and a plurality of non-through plugs extending through the semiconductor substrate from the first side to the second side.
    Type: Grant
    Filed: December 21, 2017
    Date of Patent: October 8, 2019
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventor: Po Chun Lin
  • Patent number: 10396258
    Abstract: An embodiment comprises: a substrate having a chip mounting region; first and second wiring layers disposed on the substrate around the chip mounting region so as to be spaced apart from each other; and a plurality of light emitting chips disposed on the chip mounting region, wherein the first wiring layer comprises a first wiring pattern disposed at one side of a reference line and having a first concave part, and a first extending pattern extending from the first wiring pattern to the other side of the reference line, the second wiring layer comprises a second wiring pattern disposed at the other side of the reference line and having a second concave part, and a second extending pattern extending from the second wiring pattern to one side of the reference line, and the reference line is a straight line passing through the center of the chip mounting region.
    Type: Grant
    Filed: May 13, 2015
    Date of Patent: August 27, 2019
    Assignee: LG INNOTEK CO., LTD.
    Inventors: Dae Geun Kim, Kyoung Un Kim, Seul Ki Kim, Bong Kul Min, Gyu Hyeong Bak
  • Patent number: 10388639
    Abstract: Self-aligned three dimensional vertically stacked chip stacks and processes for forming the same generally include two or more vertically stacked chips supported by a scaffolding structure, the scaffolding structure defined by a first scaffolding trench and at least one additional scaffolding trench, the first scaffolding trench comprising a bottom surface having a width and a sidewall having a height extending from the bottom surface to define a lowermost trench in a scaffolding layer, the at least one additional scaffolding trench overlaying the first scaffolding trench having a sidewall having a height and a width, wherein the width of the at least one scaffolding trench is greater than the first scaffolding trench width to define a first stair between the first scaffolding trench and the at least one additional trench; a first chip secured to the first scaffolding trench having a height less than the first scaffolding trench sidewall height; and at least one additional chip secured to and supported by the
    Type: Grant
    Filed: November 3, 2017
    Date of Patent: August 20, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Lawrence A. Clevenger, Carl J. Radens, Yiheng Xu, John H. Zhang
  • Patent number: 10388647
    Abstract: An improved transient voltage suppression device includes a semiconductor substrate, a transient voltage suppressor, at least one first diode, at least one conductive pad, and at least one second diode. The transient voltage suppressor has an N-type heavily-doped clamping area. The first anode of the first diode is electrically connected to the N-type heavily-doped clamping area. The conductive pad is electrically connected to the first cathode of the first diode. The second anode of the second diode is electrically connected to the conductive pad and the second cathode of the second diode is electrically connected to the transient voltage suppressor. The first anode is closer to the N-type heavily-doped clamping area rather than the conductive pad. The conductive pad is closer to the N-type heavily-doped clamping area rather than the second anode.
    Type: Grant
    Filed: August 20, 2018
    Date of Patent: August 20, 2019
    Assignee: Amazing Microelectronic Corp.
    Inventors: Kun-Hsien Lin, Zi-Ping Chen, Che-Hao Chuang
  • Patent number: 10361173
    Abstract: A semiconductor package assembly includes a first semiconductor package. The first semiconductor package has a semiconductor die having pads thereon, first vias disposed on the first semiconductor die, the first vias coupled to the pads. A second semiconductor package is stacked on the first semiconductor package and includes a body having a die-attach surface and a bump-attach surface opposite to the die-attach surface, a first memory die mounted on the bump-attach surface, coupled to the body, and a second memory die mounted on the die-attach surface, coupled to the body through the bonding wires. The number of input/output (I/O) pins of first memory die is different from the number of input/output (I/O) pins of the second memory die.
    Type: Grant
    Filed: November 30, 2016
    Date of Patent: July 23, 2019
    Assignee: MediaTek Inc.
    Inventors: Tzu-Hung Lin, Ming-Tzong Yang
  • Patent number: 10347617
    Abstract: Self-aligned three dimensional vertically stacked chip stacks and processes for forming the same generally include two or more vertically stacked chips supported by a scaffolding structure, the scaffolding structure defined by a first scaffolding trench and at least one additional scaffolding trench, the first scaffolding trench comprising a bottom surface having a width and a sidewall having a height extending from the bottom surface to define a lowermost trench in a scaffolding layer, the at least one additional scaffolding trench overlaying the first scaffolding trench having a sidewall having a height and a width, wherein the width of the at least one scaffolding trench is greater than the first scaffolding trench width to define a first stair between the first scaffolding trench and the at least one additional trench; a first chip secured to the first scaffolding trench having a height less than the first scaffolding trench sidewall height; and at least one additional chip secured to and supported by the
    Type: Grant
    Filed: September 5, 2017
    Date of Patent: July 9, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Lawrence A. Clevenger, Carl J. Radens, Yiheng Xu, John H. Zhang
  • Patent number: 10319701
    Abstract: An embodiment bonded integrated circuit (IC) structure includes a first IC structure and a second IC structure bonded to the first IC structure. The first IC structure includes a first bonding layer and a connector. The second IC structure includes a second bonding layer bonded to and contacting the first bonding layer and a contact pad in the second bonding layer. The connector extends past an interface between the first bonding layer and the second bonding layer, and the contact pad contacts a lateral surface and a sidewall of the connector.
    Type: Grant
    Filed: January 7, 2015
    Date of Patent: June 11, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Wen-Chih Chiou, Chung-Shi Liu
  • Patent number: 10319630
    Abstract: A plurality of metal tracks are formed in a plurality of intermetal dielectric layers stacked in an integrated circuit die. Thin protective dielectric layers are formed around the metal tracks. The protective dielectric layers act as a hard mask to define contact vias between metal tracks in the intermetal dielectric layers.
    Type: Grant
    Filed: September 27, 2012
    Date of Patent: June 11, 2019
    Assignees: STMICROELECTRONICS, INC., INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: John H. Zhang, Lawrence A. Clevenger, Carl Radens, Yiheng Xu
  • Patent number: 10308506
    Abstract: A MEMS device comprises an electro mechanical element in a sealed chamber containing a gas comprising a reactive gas selected to react with any contaminants that may be present or formed on the operating surfaces of the device in a manner to maximize the electrical conductivity of the surfaces during operation of the device. The MEMS device may comprise a MEMS switch having electrical contacts as the operating surfaces. The reactive gas may comprise hydrogen or an azane, optionally mixed with an inert gas, or any combination of the gases. The corresponding process provides a means to substantially reduce or eliminate contaminants present or formed on the operating surfaces of MEMS devices in a manner to maximize the electrical conductivity of the surfaces during operation of the devices.
    Type: Grant
    Filed: January 27, 2016
    Date of Patent: June 4, 2019
    Assignee: International Business Machines Corporation
    Inventors: John M. Cotte, Nils D. Hoivik, Christopher V. Jahnes
  • Patent number: 10304815
    Abstract: Self-aligned three dimensional vertically stacked chip stacks and processes for forming the same generally include two or more vertically stacked chips supported by a scaffolding structure, the scaffolding structure defined by a first scaffolding trench and at least one additional scaffolding trench, the first scaffolding trench comprising a bottom surface having a width and a sidewall having a height extending from the bottom surface to define a lowermost trench in a scaffolding layer, the at least one additional scaffolding trench overlaying the first scaffolding trench having a sidewall having a height and a width, wherein the width of the at least one scaffolding trench is greater than the first scaffolding trench width to define a first stair between the first scaffolding trench and the at least one additional trench; a first chip secured to the first scaffolding trench having a height less than the first scaffolding trench sidewall height; and at least one additional chip secured to and supported by the
    Type: Grant
    Filed: November 3, 2017
    Date of Patent: May 28, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Lawrence A. Clevenger, Carl J. Radens, Yiheng Xu, John H. Zhang