Abstract: According to the present disclosure, a semiconductor device includes a semiconductor chip, a frame, a projection projecting from the frame, a lead in which a projection insertion portion into which the projection is to be inserted is formed, and which directly contacts the frame to electrically connect the semiconductor chip to the frame and a first bonding material configured to bond the projection to the lead.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate having a base portion and a fin portion over the base portion. The semiconductor device structure includes an isolation layer over the base portion and surrounding the fin portion. The semiconductor device structure includes a metal gate stack over the isolation layer and wrapping around an upper part of the fin portion. The metal gate stack includes a gate dielectric layer and a metal gate electrode layer over the gate dielectric layer, and the gate dielectric layer includes fluorine. A first part of the isolation layer is not covered by the metal gate stack, the first part includes fluorine, and a first concentration of fluorine in the first part increases toward a first top surface of the first part.

Abstract: Implementations of the semiconductor package may include a first sidewall opposite a second sidewall, and a third sidewall opposite a fourth sidewall. Implementations of the semiconductor package may include a first lead and a second lead extending from the first sidewall and a first half-etched tie bar directly coupled to the first lead. An end of the first half-etched tie bar may be exposed on the third sidewall of the semiconductor package. Implementations of the semiconductor package may also include a second half-etched tie bar directly coupled to the second lead. An end of the second half-etched tie bar may be exposed on the fourth sidewall. An end of the first lead and an end of the second lead may each be electroplated. The first die flag and the second die flag may be electrically isolated from the first lead and the second lead.

Abstract: Integrated circuit assemblies may contain various mold, fill, and/or underfill materials. As these integrated circuit assemblies become ever smaller, it becomes challenging to prevent voids from forming within these materials, which may affect the reliability of the integrated circuit assemblies. Since integrated circuit assemblies are generally formed by electrically attaching integrated circuit dice on electronic substrates, the present description proposes injecting the mold, fill, and/or underfill materials through openings formed in the electronic substrate to fill voids that may form and/or to prevent the formation of the voids altogether.

Abstract: According to one embodiment, there is provided a semiconductor device including a support, multiple first chips, a first sealing portion, a second chip, multiple first terminals and a second terminal. The multiple first chips are stacked on the support. The first sealing portion seals multiple first chips and has a recessed portion including a bottom surface separated from multiple first chips on a surface opposite to the support. The second chip is disposed in the recessed portion and has a function different from a function of the first chips. The multiple first terminals correspond to multiple first chips, each of multiple first terminals extending in a stacking direction from a surface of the first chip opposite to the support and penetrating the first sealing portion. The second terminal is disposed on a surface of the second chip opposite to the support.

Abstract: A semiconductor package includes a multilayer package substrate with a top layer including top filled vias through a top dielectric layer and top metal layer providing a top surface for leads and traces connected to the leads, and a bottom layer including bottom filled vias including contact pads through a bottom dielectric and metal layer. The top filled vias are for connecting the bottom and top metal layer. The bottom metal filled vias are for connecting the bottom metal layer to the contact pads. An integrated circuit (IC) die has nodes in its circuitry connected to the bond pads. The IC die is flipchip mounted onto the leads. A passive device(s) is surface mounted by an electrically conductive material on the top metal layer electrically connected between at least one adjacent pair of the leads. A mold compound is for encapsulating at least the IC die and passive device.

Abstract: A semiconductor package includes a die attach pad; a plurality of lead terminals disposed around the die attach pad; a semiconductor die mounted on the die attach pad; a molding compound encapsulating the plurality of lead terminals, the semiconductor die, and the die attach pad; and a step cut sawn into the molding compound along a perimeter of a bottom surface of the semiconductor package. The step cut penetrates through an entire thickness of each of the plurality of lead terminals, whereby each of the plurality of lead terminals has at least an exposed outer end at the step cut.

Abstract: A semiconductor package is disclosed. In one example, the semiconductor package comprises a semiconductor chip, a molded body encapsulating the semiconductor chip and comprising a top face and an opposing bottom face and four side faces connecting the top and bottom faces, and a plurality of electrical contacts arranged on two of the side faces of the molded body, wherein the other two side faces are metal-free side faces, and wherein the molded body comprises a cut surface at no more than one of the side faces.

Abstract: A semiconductor package includes a package substrate, a semiconductor chip on the package substrate, the semiconductor chip including a logic chip and a memory stack structure on the logic chip, a connector and a connector terminal below the package substrate, a molding layer that covers the semiconductor chip, the molding layer having a recess region on a top surface of the molding layer, a housing that covers the molding layer, and an air gap on the semiconductor chip, the air gap being defined by the housing and the recess region of the molding layer, and the molding layer separating the air gap from the memory stack structure of the semiconductor chip.

Abstract: An electronic device includes first leads along a first side, second leads along a second side, first and second dies, and a magnetic assembly with a multilevel lamination structure with first and second windings and a conductive guard trace. The lamination structure includes the first winding in a first level, and the second winding in a different level. The guard trace is between the first patterned conductive feature and the second side of the package structure. A first set of electrical connections couple the first die, the first winding, and one of the first conductive leads in a first circuit, and a second set of electrical connections couple the second die, the second winding, the guard trace and one of the second conductive leads in an isolated second circuit.

Abstract: Implementations of the semiconductor package may include a first sidewall opposite a second sidewall, and a third sidewall opposite a fourth sidewall. Implementations of the semiconductor package may include a first lead and a second lead extending from the first sidewall and a first half-etched tie bar directly coupled to the first lead. An end of the first half-etched tie bar may be exposed on the third sidewall of the semiconductor package. Implementations of the semiconductor package may also include a second half-etched tie bar directly coupled to the second lead. An end of the second half-etched tie bar may be exposed on the fourth sidewall. An end of the first lead and an end of the second lead may each be electroplated. The first die flag and the second die flag may be electrically isolated from the first lead and the second lead.

Abstract: Electrical current flow in a ball grid array (BGA) package can be measured by an apparatus including an integrated circuit (IC) electrically connected to the BGA package. Solder balls connect the BGA package to a printed circuit board (PCB) and are arranged to provide a contiguous channel for a current sense wire. A subset of solder balls is electrically connected to supply current from the PCB through the BGA package to the IC. The current sense wire is attached to the upper surface of the PCB, within the contiguous channel, and surrounds the subset of solder balls. An amplifier is electrically connected to the current sense wire ends to amplify a voltage induced on the current sense wire by current flow into the BGA package. A sensing analog-to-digital converter (ADC) is electrically connected to convert a voltage at the output of the amplifier into digital output signals.

Abstract: A package includes a carrier, an electronic component on the carrier, an encapsulant encapsulating at least part of the carrier and the electronic component, and at least one lead extending beyond the encapsulant and having a punched surface, wherein at least part of at least one side flank of the encapsulant has a sawn texture.

Abstract: A package structure includes at least one semiconductor die, a plurality of hollow cylinders, an insulating encapsulant, a redistribution layer and through holes. The plurality of hollow cylinders is surrounding the at least one semiconductor die. The insulating encapsulant has a top surface and a bottom surface opposite to the top surface, wherein the insulating encapsulant encapsulates the at least one semiconductor die and the plurality of hollow cylinders. The redistribution layer is disposed on the top surface of the insulant encapsulant and over the at least one semiconductor die. The through holes are penetrating through the plurality of hollow cylinders.

Abstract: A semiconductor package comprises a lead frame, a chip, and a molding encapsulation. The lead frame comprises one or more die paddles comprising a first die paddle. The first die paddle comprises one or more through holes, one or more protrusions with grooves on top surfaces of the one or more protrusions, or one or more squeezed extensions. Each of the one or more through holes is filled with a respective portion of the molding encapsulation. Each of the one or more through holes may be of a rectangular shape, a rectangular shape with four filleted corners, a circular shape, or an oval shape. Each of the grooves is filled with a respective portion of the molding encapsulation. A respective side wall of each of the one or more squeezed extensions is of a swallowtail shape. The swallowtail shape directly contacts the molding encapsulation.

Abstract: A method of forming a chip package is provided. The method may include: arranging an elastic thermal interface material over a semiconductor chip, wherein the elastic thermal interface material may be configured to transfer heat from the chip to an outside; arranging a mold around the thermal interface material and at least partially around the semiconductor chip, thereby compressing the elastic thermal interface material with the mold; and filling the mold with a packaging material.

Abstract: A silicon carbide epitaxial layer includes a first silicon carbide layer, a second silicon carbide layer, a third silicon carbide layer, and a fourth silicon carbide layer. A nitrogen concentration of the second silicon carbide layer is increased from the first silicon carbide layer toward the third silicon carbide layer. A value obtained by dividing, by a thickness of the second silicon carbide layer, a value obtained by subtracting a nitrogen concentration of the first silicon carbide layer from a nitrogen concentration of the third silicon carbide layer is less than or equal to 6×1023 cm?4. Assuming that the nitrogen concentration of the third silicon carbide layer is N cm?3 and a thickness of the third silicon carbide layer is X ?m, X and N satisfy a Formula 1.

Abstract: The invention relates to a lead frame assembly comprising a plurality of regularly arranged lead frames, each of which is suitable for electrically contacting components, comprises at least two lead frame elements distanced laterally by a recess and which are provided as electrical connections of different polarity, and has at least one anchoring element, which is suitable for anchoring a housing body of the component, the lead frame elements being thinned, flat regions of the lead frame, and the at least one anchoring element protrudes from a plane of the lead frame elements in the form of a pillar, and a plurality of connection elements, which in each case connects two lead frame elements of adjacent lead frames to one another, the two connected lead frame elements being provided as terminals of different polarity.

Abstract: In a described example, an integrated circuit (IC) package includes an IC die disposed on a die attach pad; a plurality of leads electrically connected to terminals on the IC die, the leads including a base metal; and molding compound material encapsulating portions of the IC die, the die attach pads, and the plurality of leads; the plurality of leads having a solder joint reinforcement tab. The solder joint reinforcement tabs include a first side, a second side opposite to the first side, a third side, a fourth side opposite to and in parallel to the third side, a fifth side forming an end portion of the solder joint reinforcement tab, the solder joint reinforcement tabs including a solderable metal layer on the second, third and fourth sides and on portions of the fifth side.

Abstract: A package mold according to some embodiments includes a first mold body and a second mold body, a mold cavity in the first mold body, a gate in a first side of the mold cavity for supplying liquid mold compound into the mold cavity, a longitudinal vent for releasing gas from the mold cavity in a second side of the mold cavity opposite the first side of the mold cavity, and a transverse vent for releasing gas from the mold cavity in a third side of the mold cavity that extends between the first and second sides of the mold cavity. Methods of packaging an electronic device using the package mold and resulting packaged devices are also disclosed.