Patents Examined by Dilinh P. Nguyen
  • Patent number: 11145577
    Abstract: A system-in-package apparatus includes a square wave lead frame that provides a recess for a first semiconductive device as well as a feature for a second device. The system-in-package apparatus includes a printed wiling board that is wrapped onto the lead frame after a manner to enclose the first semiconductive device into the recess.
    Type: Grant
    Filed: December 29, 2016
    Date of Patent: October 12, 2021
    Assignee: Intel Corporation
    Inventors: Sonja Koller, Georg Seidemann, Reinhard Mahnkopf, Bernd Waidhas
  • Patent number: 11133568
    Abstract: A semiconductor package structure having an antenna module includes: a substrate, having a first surface, a second surface, and at least one via hole made by a laser running through the substrate; a rewiring layer, disposed on the first surface of the substrate; metal bumps, disposed on the rewiring layer and electrically connected to the rewiring layer; a semiconductor chip, disposed on and electrically connected to the rewiring layer; a conductive column, filling the via hole, and an antenna module, disposed on the second surface of the substrate and electrically connected to the metal bumps through the conductive column and the rewiring layer.
    Type: Grant
    Filed: December 26, 2018
    Date of Patent: September 28, 2021
    Assignee: SJ SEMICONDUCTOR (JIANGYIN) CORPORATION
    Inventors: Yenheng Chen, Chengtar Wu, Chengchung Lin
  • Patent number: 11127648
    Abstract: The present disclosure relates to a thermally enhanced package, which includes a carrier, a thinned die over the carrier, a mold compound, and a heat extractor. The thinned die includes a device layer over the carrier and a dielectric layer over the device layer. The mold compound resides over the carrier, surrounds the thinned die, and extends beyond a top surface of the thinned die to define an opening within the mold compound and over the thinned die. The top surface of the thinned die is at a bottom of the opening. At least a portion of the heat extractor is inserted into the opening and in thermal contact with the thinned die. Herein the heat extractor is formed of a metal or an alloy.
    Type: Grant
    Filed: November 29, 2018
    Date of Patent: September 21, 2021
    Assignee: Qorvo US, Inc.
    Inventors: Julio C. Costa, George Maxim
  • Patent number: 11127926
    Abstract: A method of manufacturing a display device having an organic EL device includes the steps of: forming an organic EL device over a substrate; and forming a protection film so as to cover the organic EL device. The protection film is made of a laminated film of a first insulating film containing Si, a second insulating film containing Al and a third insulating film containing Si. The step of forming the protection film includes the steps of: forming the first insulating film by a plasma CVD method so as to cover the organic EL device; forming the second insulating film over the first insulating film by an ALD method; and forming the third insulating film over the second insulating film by a plasma CVD method.
    Type: Grant
    Filed: November 27, 2016
    Date of Patent: September 21, 2021
    Assignee: THE JAPAN STEEL WORKS, LTD.
    Inventors: Keisuke Washio, Tatsuya Matsumoto, Junichi Shida, Takashi Ebisawa
  • Patent number: 11111136
    Abstract: A MEMS device comprises an electro mechanical element in a sealed chamber containing a gas comprising a reactive gas selected to react with any contaminants that may be present or formed on the operating surfaces of the device in a manner to maximize the electrical conductivity of the surfaces during operation of the device. The MEMS device may comprise a MEMS switch having electrical contacts as the operating surfaces. The reactive gas may comprise hydrogen or an azane, optionally mixed with an inert gas, or any combination of the gases. The corresponding process provides a means to substantially reduce or eliminate contaminants present or formed on the operating surfaces of MEMS devices in a manner to maximize the electrical conductivity of the surfaces during operation of the devices.
    Type: Grant
    Filed: September 8, 2017
    Date of Patent: September 7, 2021
    Assignee: International Business Machines Corporation
    Inventors: John M. Cotte, Nils D. Hoivik, Christopher V. Jahnes
  • Patent number: 11107801
    Abstract: A package structure and method for forming the same are provided. The package structure includes a first redistribution structure formed over a substrate, and the first redistribution structure includes a first conductive line, a second conductive line and a first overlapping conductive line between the first conductive line and the second conductive line. The first conductive line has a first width, the second conductive line which is parallel to the first conductive line has a second width, and the overlapping conductive line has a third width which is greater than the first width and the second width. The package structure includes a first package unit formed over the first redistribution structure, and the first package unit includes a first semiconductor die and a first die stack, and the first semiconductor die has a different function than the first die stack.
    Type: Grant
    Filed: December 27, 2018
    Date of Patent: August 31, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Shin-Puu Jeng, Po-Yao Lin, Shuo-Mao Chen, Feng-Cheng Hsu, Chia-Hsiang Lin
  • Patent number: 11094634
    Abstract: A semiconductor package structure and manufacturing method thereof are provided. The semiconductor package structure includes a package structure and a rigid-flexible substrate. The package structure includes semiconductor dies, a molding compound and a redistribution layer. The molding compound laterally encapsulates the semiconductor dies. The redistribution layer is disposed at a front side of the semiconductor dies and electrically connected to the semiconductor dies. The rigid-flexible substrate is disposed at a side of the redistribution layer opposite to the semiconductor dies, and includes rigid structures, a flexible core and a circuit layer. The rigid structures respectively have an interconnection structure therein. The interconnection structures are electrically connected to the redistribution layer. The flexible core laterally penetrates and connects the rigid structures.
    Type: Grant
    Filed: December 24, 2018
    Date of Patent: August 17, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chuei-Tang Wang, Chen-Hua Yu, Chung-Shi Liu, Chih-Yuan Chang, Jiun-Yi Wu, Jeng-Shien Hsieh, Tin-Hao Kuo
  • Patent number: 11088123
    Abstract: Aspects of the disclosure provide a package system that includes a first integrated circuit (IC) package and a second IC package. The first IC package includes a first IC chip mounted on a first substrate-chip surface of a first package substrate. The first package substrate includes first near-conductive layers that are closer to the first substrate-chip surface than first far-conductive layers. The second IC package includes a second IC chip mounted on a second substrate-chip surface of a second package substrate. The second package substrate includes second near-conductive layers that are closer to the second substrate-chip surface than second far-conductive layers. A first contact structure on the first substrate-chip surface and a second contact structure on the second substrate-chip surface electrically couple the first IC chip with the second IC chip through electrical connections in the first and second near-conductive layers.
    Type: Grant
    Filed: May 15, 2019
    Date of Patent: August 10, 2021
    Assignee: Marvell Israel (M.I.S.L) Ltd.
    Inventors: Dan Azeroual, Ronen Sinai
  • Patent number: 11088053
    Abstract: The invention discloses an encapsulation structure with high density, multiple sided and exposed leads and method for manufacturing the same. The encapsulation structure includes a package, a die pad and a plurality of leads, wherein the die pad and the leads are disposed at a bottom of the package; bottom surfaces of the leads expose in a bottom surface of the package, and the leads extends towards multiple sides of the package until beyond the package; the package includes an integrated circuit provided on the die pad and connected with the leads, and a plastic package for packaging the integrated circuit, the die pad and the leads; a bottom surface of the die pad and the bottom surfaces of the leads are provided on the same horizontal plane; the leads comprise a first lead distant from the die pad.
    Type: Grant
    Filed: January 9, 2020
    Date of Patent: August 10, 2021
    Assignee: GUANGDONG CHIPPACKING TECHNOLOGY CO., LTD.
    Inventors: Xilin Rao, Zhengguo Wen, Jianwei Yang, Yiwei Huang, Yiping Si, Fangbiao Liu
  • Patent number: 11081418
    Abstract: The present disclosure relates to a thermally enhanced package, which includes a carrier, a thinned die over the carrier, a mold compound, and a heat extractor. The thinned die includes a device layer over the carrier and a dielectric layer over the device layer. The mold compound resides over the carrier, surrounds the thinned die, and extends beyond a top surface of the thinned die to define an opening within the mold compound and over the thinned die. The top surface of the thinned die is at a bottom of the opening. At least a portion of the heat extractor is inserted into the opening and in thermal contact with the thinned die. Herein the heat extractor is formed of a metal or an alloy.
    Type: Grant
    Filed: November 29, 2018
    Date of Patent: August 3, 2021
    Assignee: Qorvo US, Inc.
    Inventors: Julio C. Costa, George Maxim
  • Patent number: 11069778
    Abstract: A method for producing a silicon carbide component includes forming a silicon carbide layer on an initial wafer, forming a doping region of the silicon carbide component to be produced in the silicon carbide layer, and forming an electrically conductive contact structure of the silicon carbide component to be produced on a surface of the silicon carbide layer. The electrically conductive contact structure electrically contacts the doping region. Furthermore, the method includes splitting the silicon carbide layer or the initial wafer after forming the electrically conductive contact structure, such that a silicon carbide substrate at least of the silicon carbide component to be produced is split off.
    Type: Grant
    Filed: August 24, 2018
    Date of Patent: July 20, 2021
    Assignee: Infineon Technologies AG
    Inventors: Roland Rupp, Ronny Kern
  • Patent number: 11069602
    Abstract: The present invention is a semiconductor module including: first and second drive circuits that perform drive control of at least one pair of first and second switching devices, in which the at least one pair of first and second switching devices and the first and second drive circuits are sealed in a package having a rectangular shape in plan view, and there are provided: a control terminal provided to protrude from a side surface of a first long side out of first and second long sides of the package, and to which a control signal of the first and second drive circuits is inputted; an output terminal provided to protrude from a side surface of the second long side; a first main terminal provided to protrude from a side surface of a first short side out of first and second short sides of the package; and a second main terminal provided to protrude from a side surface of the second short side.
    Type: Grant
    Filed: November 22, 2016
    Date of Patent: July 20, 2021
    Assignee: Mitsubishi Electric Corporation
    Inventors: Shuhei Yokoyama, Shogo Shibata, Maki Hasegawa, Koichiro Noguchi, Shigeru Mori, Toru Iwagami
  • Patent number: 11069705
    Abstract: The present disclosure provides a three-dimensional (3D) memory device and a method for forming the same. The 3D memory device can comprise a channel structure region including a plurality of channel structures; a first staircase structure in a first staircase region including a plurality of division block structures arranged along a first direction on a first side of the channel structure, and a second staircase structure in a second staircase region including a plurality of division block structures arranged along the first direction on a second side of the channel structure. A first vertical offset defines a boundary between adjacent division block structures. Each division block structure includes a plurality of staircases arranged along a second direction that is different from the first direction. Each staircase includes a plurality of steps arranged along the first direction.
    Type: Grant
    Filed: July 1, 2019
    Date of Patent: July 20, 2021
    Assignee: Yangtze Memory Technologies Co., Ltd.
    Inventors: Zhong Zhang, Wenyu Hua, Zhiliang Xia
  • Patent number: 11069655
    Abstract: A semiconductor device includes a composite chip mounted over a wiring substrate, the composite chip including a first area, a second area that is provided independently from the first area, and a third area including a first material between the first and second areas. The first area includes a first circuit formed in the first area, and the second area includes a second circuit formed in the second area. The first area is spaced apart from the second area by the first material.
    Type: Grant
    Filed: November 17, 2017
    Date of Patent: July 20, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Sensho Usami, Kazuhiko Shibata, Yutaka Kagaya
  • Patent number: 11062975
    Abstract: Package structures and methods of forming the same are disclosed. The package structure includes a package, a device and a screw. The package includes a plurality of dies, an encapsulant encapsulating the plurality of dies, and a redistribution structure over the plurality of dies and the encapsulant. The device is disposed over the package, wherein the dies and the encapsulant are disposed between the device and the redistribution structure. The screw penetrates through the package and the device.
    Type: Grant
    Filed: December 25, 2018
    Date of Patent: July 13, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Chia Lai, Chen-Hua Yu, Chung-Shi Liu, Hao-Yi Tsai, Kuo-Chung Yee, Tin-Hao Kuo
  • Patent number: 11049845
    Abstract: A semiconductor device comprises the following: a wiring substrate having on one side a recessed section and a plurality of connection pads; a first semiconductor chip mounted in the recessed section; a second semiconductor chip that has a plurality of electrode pads on the surface of at least one end section (in this case, both ends) and that is laminated onto the first semiconductor chip so that at least one end section (in this case, both ends) protrudes from the first semiconductor chip; a plurality of wires that mutually and electrically connect the plurality of connection pads of the wiring substrate and the plurality of electrode pads of the second semiconductor chip. One end section of the second semiconductor chip extends beyond the inner surface of the recessed section and is supported by one side of the wiring substrate.
    Type: Grant
    Filed: September 4, 2013
    Date of Patent: June 29, 2021
    Assignee: LONGITUDE LICENSING LIMITED
    Inventors: Takashi Ohba, Yoshihiro Sato
  • Patent number: 11043439
    Abstract: The present disclosure relates to a thermally enhanced package, which includes a carrier, a thinned die over the carrier, a mold compound, and a heat extractor. The thinned die includes a device layer over the carrier and a dielectric layer over the device layer. The mold compound resides over the carrier, surrounds the thinned die, and extends beyond a top surface of the thinned die to define an opening within the mold compound and over the thinned die. The top surface of the thinned die is at a bottom of the opening. At least a portion of the heat extractor is inserted into the opening and in thermal contact with the thinned die. Herein the heat extractor is formed of a metal or an alloy.
    Type: Grant
    Filed: November 29, 2018
    Date of Patent: June 22, 2021
    Assignee: Qorvo US, Inc.
    Inventors: Julio C. Costa, George Maxim
  • Patent number: 11043530
    Abstract: A light-emitting component includes a light-emitting element, a driving thyristor, and a light-absorbing layer. The light-emitting element emits light of a predetermined wavelength. The driving thyristor causes the light-emitting element to emit light or causes an amount of light emitted by the light-emitting element to increase, upon entering an on-state. The light-absorbing layer is disposed between the light-emitting element and the driving thyristor such that the light-emitting element and the driving thyristor are stacked, and absorbs light emitted by the driving thyristor.
    Type: Grant
    Filed: February 8, 2018
    Date of Patent: June 22, 2021
    Assignee: FUJIFILM Business Innovation Corp.
    Inventor: Takashi Kondo
  • Patent number: 11031311
    Abstract: In a described example, a packaged semiconductor device includes: a semiconductor die with a component proximate to a surface of the semiconductor die; the semiconductor die mounted on a substrate. The component is covered with a first polymer layer with a first modulus and at least a portion of the first polymer layer is covered by at least one second polymer layer with a second modulus and the second modulus is greater than the first modulus. The semiconductor die and a portion of the substrate are covered with mold compound.
    Type: Grant
    Filed: November 21, 2018
    Date of Patent: June 8, 2021
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventor: Luu Thanh Nguyen
  • Patent number: 11018040
    Abstract: An electronic device structure and a method for making an electronic device. As non-limiting examples, various aspects of this disclosure provide a method of manufacturing an electronic device that comprises the utilization of a carrier assisted substrate, and an electronic device manufactured thereby.
    Type: Grant
    Filed: June 19, 2019
    Date of Patent: May 25, 2021
    Assignee: Amkor Technology Singapore Holding Pte. Ltd.
    Inventors: Roger St. Amand, Young Do Kweon