Patents Examined by Dilinh P. Nguyen
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Patent number: 11371951Abstract: A gas sensor comprises a set of one or more sensor cells (SC) and a substrate (1). Each sensor cell (SC) of the set comprises a sensitive film (42) built from a sensitive material (4) covering an area of the substrate (1). One or more elevated structures (2) are manufactured in or around said area for preventing the sensitive material (4) to expand when being applied thereto.Type: GrantFiled: June 2, 2014Date of Patent: June 28, 2022Assignee: Sensirion AGInventors: Felix Mayer, Markus Graf, Lukas Burgi, Martina Hitzbleck, Ulrich Muecke
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Patent number: 11367675Abstract: A method for manufacturing a semiconductor device includes: fixing a semiconductor chip to a first part of a leadframe; bonding one connector member to a first terminal of the semiconductor chip, a second terminal of the semiconductor chip, a second part of the leadframe, and a third part of the leadframe; forming a sealing member; and separating a first conductive part of the connector member and a second conductive part of the connector member by removing at least a section of the portion of the connector member exposed outside the sealing member, the first conductive part being bonded to the first terminal and the second part, the second conductive part being bonded to the second terminal and the third part.Type: GrantFiled: December 3, 2020Date of Patent: June 21, 2022Assignees: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATIONInventors: Katsuya Sato, Kakeru Yamaguchi, Tetsuya Yamamoto
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Patent number: 11362022Abstract: A multichip package and a method for manufacturing the same are provided. A multichip package includes: a plurality of semiconductor chips each mounted on corresponding lead frame pads; lead frames connected to the semiconductor chips by a bonding wire; and fixed frames integrally formed with at least one of the lead frame pads and configured to support the lead frame pads on a package-forming substrate.Type: GrantFiled: May 2, 2013Date of Patent: June 14, 2022Assignee: MagnaChip Semiconductor, Ltd.Inventor: Hyun Dong Kim
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Patent number: 11348806Abstract: A method of making Flat No-Lead Packages with plated lead surfaces exposed on lateral faces thereof. The method includes providing a plurality of Flat No-Lead Packages having severed, unplated lead surfaces exposed on lateral faces thereof and having plated lead surfaces exposed on bottom faces thereof. The method further includes batch electroplating the severed unplated lead surfaces of the plurality of Flat No-Lead Packages.Type: GrantFiled: December 23, 2014Date of Patent: May 31, 2022Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Lee Han Meng@ Eugene Lee, Shu Hui Ooi, Anis Fauzi Abdul Aziz, Wei Fen Sueann Lim
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Patent number: 11348938Abstract: In a method of manufacturing a vertical memory device, a first sacrificial layer including a nitride is formed on a substrate. A mold including an insulation layer and a second sacrificial layer alternately and repeatedly stacked on the first sacrificial layer is formed. The insulation layer and the second sacrificial layer include a first oxide and a second oxide, respectively. A channel is formed through the mold and the first sacrificial layer. An opening is formed through the mold and the first sacrificial layer to expose an upper surface of the substrate. The first sacrificial layer is removed through the opening to form a first gap. A channel connecting pattern is formed to fill the first gap. The second sacrificial layer is replaced with a gate electrode.Type: GrantFiled: June 19, 2019Date of Patent: May 31, 2022Inventors: Il-Woo Kim, Sang-Gi An, Hyun-Gon Pyo, Ik-Soo Kim, Hee-Sook Park, Ji-Woon Im
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Patent number: 11342295Abstract: A package structure includes at least one semiconductor die, a plurality of hollow cylinders, an insulating encapsulant, a redistribution layer and through holes. The plurality of hollow cylinders is surrounding the at least one semiconductor die. The insulating encapsulant has a top surface and a bottom surface opposite to the top surface, wherein the insulating encapsulant encapsulates the at least one semiconductor die and the plurality of hollow cylinders. The redistribution layer is disposed on the top surface of the insulant encapsulant and over the at least one semiconductor die. The through holes are penetrating through the plurality of hollow cylinders.Type: GrantFiled: December 24, 2018Date of Patent: May 24, 2022Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chen-Hua Yu, Chung-Shi Liu, Hao-Yi Tsai, Tin-Hao Kuo
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Patent number: 11329166Abstract: In a transistor that includes an oxide semiconductor, a change in electrical characteristics is suppressed and the reliability is improved. A semiconductor device that includes a transistor is provided. The transistor includes a first conductive film that functions as a first gate electrode, a first gate insulating film, a first oxide semiconductor film that includes a channel region, a second gate insulating film, and a second oxide semiconductor film and a second conductive film that function as a second gate electrode. The second oxide semiconductor film includes a region higher in carrier density than the first oxide semiconductor film. The second conductive film includes a region in contact with the first conductive film.Type: GrantFiled: November 9, 2016Date of Patent: May 10, 2022Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Yasuharu Hosaka, Yukinori Shima, Masataka Nakada, Masami Jintyou
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Patent number: 11328974Abstract: The present disclosure relates to a thermally enhanced package, which includes a carrier, a thinned die over the carrier, a mold compound, and a heat extractor. The thinned die includes a device layer over the carrier and a dielectric layer over the device layer. The mold compound resides over the carrier, surrounds the thinned die, and extends beyond a top surface of the thinned die to define an opening within the mold compound and over the thinned die. The top surface of the thinned die is at a bottom of the opening. At least a portion of the heat extractor is inserted into the opening and in thermal contact with the thinned die. Herein the heat extractor is formed of a metal or an alloy.Type: GrantFiled: November 29, 2018Date of Patent: May 10, 2022Assignee: Qorvo US, Inc.Inventors: Julio C. Costa, George Maxim
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Patent number: 11322396Abstract: A semiconductor device includes a substrate, a first conductive feature over a portion of the substrate, and an etch stop layer over the substrate and the first conductive feature. The etch stop layer includes a silicon-containing dielectric (SCD) layer and a metal-containing dielectric (MCD) layer over the SCD layer. The semiconductor device further includes a dielectric layer over the etch stop layer, and a second conductive feature in the dielectric layer. The second conductive feature penetrates the etch stop layer and electrically connects to the first conductive feature.Type: GrantFiled: July 24, 2018Date of Patent: May 3, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Szu-Ping Tung, Jen Hung Wang, Shing-Chyang Pan
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Patent number: 11315833Abstract: A wafer processing method includes a sheet bonding step of placing a polyolefin or polyester sheet on a front side of a wafer having a device area where devices are formed so as to be separated by division lines, the sheet having a size capable of covering the device area, and next performing thermocompression bonding to bond the sheet to the front side of the wafer, thereby protecting the front side of the wafer with the sheet. The method further includes a test element group (TEG) cutting step of applying a first laser beam through the sheet to the wafer along each division line thereby cutting a TEG formed on each division line, and a modified layer forming step of applying a second laser beam to a back side of the wafer along each division line, the second laser beam having a transmission wavelength to the wafer, thereby forming a modified layer inside the wafer along each division line.Type: GrantFiled: June 19, 2019Date of Patent: April 26, 2022Assignee: DISCO CORPORATIONInventor: Jinyan Zhao
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Patent number: 11309234Abstract: A semiconductor device includes: an oscillator including external terminals disposed on a first face with a specific distance along a first direction; an integrated circuit including a first region formed with first electrode pads along one side, and a second region formed with second electrode pads on two opposing sides of the first region; a lead frame that includes terminals at a peripheral portion, and on which the oscillator and the integrated circuit are mounted such that the external terminals, the first and second electrode pads face in a substantially same direction and such that one side of the integrated circuit is substantially parallel to the first direction; a first bonding wire that connects one external terminal to one first electrode pad; a second bonding wire that connects one terminal of one lead frame to one second electrode pad; and a sealing member that seals all of the components.Type: GrantFiled: April 6, 2020Date of Patent: April 19, 2022Assignee: LAPIS SEMICONDUCTOR CO., LTD.Inventors: Toshihisa Sone, Kazuya Yamada, Akihiro Takei, Yuichi Yoshida, Kengo Takemasa
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Patent number: 11309188Abstract: A method of singulating a silicon carbide (SiC) semiconductor wafer can include defining a cut within the silicon carbide (SiC) semiconductor wafer by performing a partial dicing operation where the SiC semiconductor wafer is aligned along a plane and the cut has a depth less than a first thickness of the SiC semiconductor wafer. The cut is aligned along a vertical direction orthogonal to the plane such that a portion of the SiC semiconductor wafer has a second thickness that extends between a bottom of the cut and an outer surface of the SiC semiconductor wafer. The method can further include defining a cleave, by performing a cleaving operation, through the portion of the SiC semiconductor wafer having the second thickness. The cleave can be aligned with the cut and extending to the outer surface of the SiC semiconductor wafer.Type: GrantFiled: May 9, 2018Date of Patent: April 19, 2022Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventor: Aira Lourdes Villamor
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Patent number: 11302785Abstract: In a described example, an apparatus includes a transistor formed on a semiconductor substrate, the transistor including: a transistor gate and an extended drain between the transistor gate and a transistor drain contact; a transistor source contact coupled to a source contact probe pad; a first dielectric layer covering the semiconductor substrate and the transistor gate; a source field plate on the first dielectric layer and coupled to a source field plate probe pad spaced from and electrically isolated from the source contact probe pad; and the source field plate capacitively coupled through the first dielectric layer to a first portion of the extended drain.Type: GrantFiled: June 18, 2019Date of Patent: April 12, 2022Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Ramana Tadepalli, Chang Soo Suh
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Patent number: 11296003Abstract: The present disclosure relates to a thermally enhanced package, which includes a carrier, a thinned die over the carrier, a mold compound, and a heat extractor. The thinned die includes a device layer over the carrier and a dielectric layer over the device layer. The mold compound resides over the carrier, surrounds the thinned die, and extends beyond a top surface of the thinned die to define an opening within the mold compound and over the thinned die. The top surface of the thinned die is at a bottom of the opening. At least a portion of the heat extractor is inserted into the opening and in thermal contact with the thinned die. Herein the heat extractor is formed of a metal or an alloy.Type: GrantFiled: November 29, 2018Date of Patent: April 5, 2022Assignee: Qorvo US, Inc.Inventors: Julio C. Costa, George Maxim
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Patent number: 11289570Abstract: Systems and methods of the disclosed embodiments include a semiconductor device having a semiconductor substrate. The semiconductor substrate has a first major surface, an opposing second major surface, a first doped region of a first conductivity type disposed beneath the first major surface, and a semiconductor region of the first conductivity type disposed between the first doped region and the second major surface. The semiconductor device may also include a trench isolation structure, comprising a conductive trench filling enclosed by an insulating trench liner. The trench isolation structure extends from the first major surface through the first doped region and into the semiconductor region. The semiconductor device may also include a semiconductor device structure disposed with a drain structure, and a connection structure formed between the conductive trench filling of the trench isolation structure and the drain region.Type: GrantFiled: August 24, 2018Date of Patent: March 29, 2022Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Johan Camiel Julia Janssens, Jaroslav Pjencak, Moshe Agam
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Patent number: 11289401Abstract: A semiconductor package and a manufacturing method thereof are provided. The semiconductor package includes a semiconductor die, an encapsulant, a redistribution layer, a polymer pattern and a heat dissipation structure. The semiconductor die has conductive pads at its active side, and is laterally encapsulated by the encapsulant. The redistribution layer is disposed at the active side of the semiconductor die, and spans over a front surface of the encapsulant. The redistribution layer is electrically connected with the conductive pads. The polymer pattern is disposed at a back surface of the encapsulant that is facing away from the front surface of the encapsulant. The semiconductor die is surrounded by the polymer pattern. The heat dissipation structure is in contact with a back side of the semiconductor die that is facing away from the active side, and extends onto the polymer pattern.Type: GrantFiled: May 15, 2019Date of Patent: March 29, 2022Assignee: Powertech Technology Inc.Inventor: Kun-Yung Huang
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Patent number: 11264473Abstract: A method of manufacturing a split-gate type nonvolatile memory improving reliability and manufacturing yield. In a method of manufacturing a split-gate type nonvolatile memory in which a memory gate electrode is formed prior to a control gate electrode, a protective film is formed to cover the gate insulating film exposed between control gate electrodes before unnecessary control gate electrodes are removed.Type: GrantFiled: June 18, 2019Date of Patent: March 1, 2022Assignee: RENESAS ELECTRONICS CORPORATIONInventor: Toshiya Saitoh
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Patent number: 11264593Abstract: A flexible display device and a method for manufacturing the flexible display device are provided by embodiments of the present application, which solve problems that a module of a flexible active-matrix organic light emitting diode has a poor moisture and oxygen blocking effect on a side, and an edge is prone to fracture or be peeled off when bent. A flexible display device provided by an embodiment of the application includes a display substrate, and an encapsulating film layer disposed on a surface of the display substrate. An edge of the encapsulating film layer includes a concave-convex sawtooth structure.Type: GrantFiled: July 19, 2019Date of Patent: March 1, 2022Assignee: KunShan Go-Visionox Opto-Electronics Co., Ltd.Inventor: Yu Gu
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Patent number: 11239201Abstract: An embodiment bonded integrated circuit (IC) structure includes a first IC structure and a second IC structure bonded to the first IC structure. The first IC structure includes a first bonding layer and a connector. The second IC structure includes a second bonding layer bonded to and contacting the first bonding layer and a contact pad in the second bonding layer. The connector extends past an interface between the first bonding layer and the second bonding layer, and the contact pad contacts a lateral surface and a sidewall of the connector.Type: GrantFiled: June 10, 2019Date of Patent: February 1, 2022Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chen-Hua Yu, Wen-Chih Chiou, Chung-Shi Liu
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Patent number: 11239199Abstract: Embodiments are generally directed to package stacking using chip to wafer bonding. An embodiment of a device includes a first stacked layer including one or more semiconductor dies, components or both, the first stacked layer further including a first dielectric layer, the first stacked layer being thinned to a first thickness; and a second stacked layer of one or more semiconductor dies, components, or both, the second stacked layer further including a second dielectric layer, the second stacked layer being fabricated on the first stacked layer.Type: GrantFiled: December 26, 2015Date of Patent: February 1, 2022Assignee: Intel CorporationInventors: Georg Seidemann, Klaus Reingruber, Christian Geissler, Sven Albers, Andreas Wolter, Marc Dittes, Richard Patten