Abstract: Electrical current flow in a ball grid array (BGA) package can be measured by an apparatus including an integrated circuit (IC) electrically connected to the BGA package. Solder balls connect the BGA package to a printed circuit board (PCB) and are arranged to provide a contiguous channel for a current sense wire. A subset of solder balls is electrically connected to supply current from the PCB through the BGA package to the IC. The current sense wire is attached to the upper surface of the PCB, within the contiguous channel, and surrounds the subset of solder balls. An amplifier is electrically connected to the current sense wire ends to amplify a voltage induced on the current sense wire by current flow into the BGA package. A sensing analog-to-digital converter (ADC) is electrically connected to convert a voltage at the output of the amplifier into digital output signals.

Abstract: A quad flat no-lead (QFN) package structure including a lead frame, a semiconductor die, and an encapsulating material. The lead frame includes a die pad and a plurality of contacts surrounding the die pad. The semiconductor die is disposed on the die pad and electrically connected to the plurality of contacts, wherein a shortest distance between the semiconductor die and a first side of the die pad is shorter than a shortest distance between the semiconductor die to a second side of the die pad, and the first side is opposite to the second side. The encapsulating material encapsulates the lead frame and the semiconductor die and partially exposing the plurality of contacts, wherein an aspect ratio of the QFN package is substantially equal to or greater than 3.

Abstract: A package structure includes a metal member and a resin member. The metal member has an obverse surface facing one side in a first direction. The resin member is disposed in contact with at least a portion of the obverse surface. The obverse surface has a roughened area. The roughened area includes a plurality of first trenches recessed from the obverse surface, each of the first trenches having a surface with a greater roughness than the obverse surface. The plurality of first trenches extend in a second direction perpendicular to the first direction and are next to each other in a third direction perpendicular to the first direction and the second direction. The plurality of first trenches are filled up with the resin member.

Abstract: A packaged electronic device includes a die pad directly connected to a first set of conductive leads of a leadframe structure, a semiconductor die attached to the conductive die pad, a conductive support structure directly connected to a second set of conductive leads, and spaced apart from all other conductive structures of the leadframe structure. A magnetic assembly is attached to the conductive support structure, and a molded package structure that encloses the conductive die pad, the conductive support structure, the semiconductor die, the magnetic assembly and portions of the conductive leads, the molded package structure including a top side, and an opposite bottom side, wherein the lamination structure is centered between the top and bottom sides.

Abstract: An object of the present invention is to provide a power semiconductor device capable of improving seismic resistance while suppressing a decrease in assembly efficiency. According to the present invention, a power semiconductor device 1 includes an element installation conductor 2 including a first conductor portion 20a that is made of metal and is used for installing a power semiconductor element 300, a second conductor portion 20b that is made of metal and forms one or more main terminals 2a for transmitting a current to the power semiconductor element 300, and one or more control terminals 2b for transmitting a switching control signal to the power semiconductor element 300, and a third conductor portion 20c that is made of metal and is provided at a tip portion of the control terminal 2b.

Abstract: The present disclosure relates to a thermally enhanced package, which includes a carrier, a thinned die over the carrier, a mold compound, and a heat extractor. The thinned die includes a device layer over the carrier and a dielectric layer over the device layer. The mold compound resides over the carrier, surrounds the thinned die, and extends beyond a top surface of the thinned die to define an opening within the mold compound and over the thinned die. The top surface of the thinned die is at a bottom of the opening. At least a portion of the heat extractor is inserted into the opening and in thermal contact with the thinned die. Herein the heat extractor is formed of a metal or an alloy.

Abstract: A power semiconductor module includes an insulating substrate, a first conductive circuit pattern, a second conductive circuit pattern, a first semiconductor device, a second semiconductor device, a sealing member, and a first barrier layer. The sealing member seals the first semiconductor device, the second semiconductor device, the first conductive circuit pattern, and the second conductive circuit pattern. At least one of the first barrier layer and the sealing member includes a first stress relaxation portion. This configuration improves the reliability of the power semiconductor module.

Abstract: A device is provided. The device includes a bridge layer over a first substrate. A first connector electrically connecting the bridge layer to the first substrate. A first die is coupled to the bridge layer and the first substrate, and a second die is coupled to the bridge layer.

Abstract: A semiconductor package includes: a frame having a cavity and including a wiring structure connecting first and second surfaces of the frame; a first connection structure on the first surface of the frame and including a first redistribution layer connected to the wiring structure; a first semiconductor chip on the first connection structure within the cavity; an encapsulant encapsulating the first semiconductor chip and covering the second surface of the frame; a second connection structure including a second redistribution layer including a first redistribution pattern and first connection vias; and a second semiconductor chip disposed on the second connection structure and having connection pads connected to the second redistribution layer.

Abstract: Detection accuracy of a collector sense in detecting a voltage is improved. A power module 300 has a first conductor 410 and a second conductor 411 to which a plurality of active elements 317 and 315 configuring upper and lower arm circuits are connected. In addition, the power module 300 has an AC side terminal 320B protruding from one side 301a, a positive electrode side terminal 315B and a negative electrode side terminal 319B which protrude from the other side 301b, an intermediate electrode portion 414 that connects the first conductor 410 and the second conductor 411 to each other, and a collector sense wiring 452a in which a collector electrode of an active element 157 and the first conductor 410 are connected to each other via a sense connection portion 415.

Abstract: A semiconductor package includes a frame having a wiring structure and having a recess portion, a semiconductor chip having an active surface with a connection pad disposed thereon and disposed in the recess portion, an encapsulant sealing the semiconductor chip, and a redistribution layer having a first via connected to the connection and a second via connected to a portion of the wiring structure. The semiconductor chip includes a protective insulating film disposed on the active surface and having an opening exposing a region of the connection pad, and a redistribution capping layer connected to the region of the connection pad and extending onto the protective insulating film, and a surface of the redistribution capping layer is substantially the same level as a surface of the portion of the wiring structure, exposed from the first surface.

Abstract: The present disclosure describes a method that prevents pre-mature de-chucking in processing modules. The method includes placing a wafer onto a chuck equipped with lift pins. One or more of the lift pins include a pressure sensor configured to measure a pressure exerted by the wafer. The method further includes measuring a first pressure applied to the one or more lift pins by the wafer, lowering the lift pins to place the wafer on the chuck, and processing the wafer. The method also includes removing the wafer from the chuck by pressing the one or more lift pins against the wafer to measure a second pressure exerted by the wafer. If the measured second pressure is equal to the first pressure, the method raises the wafer using the lift pins above the chuck.

Abstract: Performance of a semiconductor device is improved. In one embodiment, for example, deposition time is increased from 4.6 sec to 6.9 sec. In other words, in one embodiment, thickness of a tantalum nitride film is increased by increasing the deposition time. Specifically, in one embodiment, deposition time is increased such that a tantalum nitride film provided on the bottom of a connection hole to be coupled to a wide interconnection has a thickness within a range from 5 to 10 nm.

Abstract: The present disclosure relates to a thermally enhanced package, which includes a carrier, a thinned die over the carrier, a mold compound, and a heat extractor. The thinned die includes a device layer over the carrier and a dielectric layer over the device layer. The mold compound resides over the carrier, surrounds the thinned die, and extends beyond a top surface of the thinned die to define an opening within the mold compound and over the thinned die. The top surface of the thinned die is at a bottom of the opening. At least a portion of the heat extractor is inserted into the opening and in thermal contact with the thinned die. Herein the heat extractor is formed of a metal or an alloy.

Abstract: A packaging structure includes a semiconductor chip and conductive connection pillars. Each of the conductive connection pillars has a first surface and a second surface opposite to the first surface, and the first surfaces of the conductive connection pillars are fixed to a surface of the semiconductor chip. The packaging structure also includes a carrier plate. The carrier plate is disposed opposite to the semiconductor chip. The conductive connection pillars are located between the semiconductor chip and the carrier plate, and the second surfaces face the carrier plate. The packaging structure further includes solder layers located between the carrier plate and the second surfaces, and a barrier layer located on the surface of the carrier plate around the solder layers.

Abstract: The present disclosure relates to a thermally enhanced package, which includes a carrier, a thinned die over the carrier, a mold compound, and a heat extractor. The thinned die includes a device layer over the carrier and a dielectric layer over the device layer. The mold compound resides over the carrier, surrounds the thinned die, and extends beyond a top surface of the thinned die to define an opening within the mold compound and over the thinned die. The top surface of the thinned die is at a bottom of the opening. At least a portion of the heat extractor is inserted into the opening and in thermal contact with the thinned die. Herein the heat extractor is formed of a metal or an alloy.

Abstract: An integrated circuit structure includes a metal pad, a passivation layer including a portion over the metal pad, a first polymer layer over the passivation layer, and a first Post-Passivation Interconnect (PPI) extending into to the first polymer layer. The first PPI is electrically connected to the metal pad. A dummy metal pad is located in the first polymer layer. A second polymer layer is overlying the first polymer layer, the dummy metal pad, and the first PPI. An Under-Bump-Metallurgy (UBM) extends into the second polymer layer to electrically couple to the dummy metal pad.

Abstract: A semiconductor substrate and a manufacturing method thereof are provided. The semiconductor substrate includes a dielectric layer, a circuit layer, a first protection layer and a plurality of conductive posts. The dielectric layer has a first surface and a second surface that are opposite to each other. The circuit layer is embedded in the dielectric layer and is exposed from the first surface. The first protection layer covers a portion of the first circuit layer and defines a plurality of holes that expose a remaining portion of the first circuit layer. The conductive posts are formed in the holes.

Abstract: A power module including a carrier assembly and a power device disposed on the carrier assembly is provided. The carrier assembly includes a bottom board, a circuit board, a lead frame, and a pad group. The circuit board is disposed on the bottom board and includes a device mounting portion and an extending portion protruding from a side of the device mounting portion. The lead frame disposed on the bottom board includes a first conductive portion and a second conductive portion insulated from each other. The extending portion of the circuit board is disposed between the first and second conductive portions, and an upper surface of the lead frame is flush with a top surface of the extending portion. A pad group includes a first pad disposed on the extending portion, a second pad and a third pad respectively disposed on the first and second conductive portions.

Abstract: A gas sensor comprises a set of one or more sensor cells (SC) and a substrate (1). Each sensor cell (SC) of the set comprises a sensitive film (42) built from a sensitive material (4) covering an area of the substrate (1). One or more elevated structures (2) are manufactured in or around said area for preventing the sensitive material (4) to expand when being applied thereto.