Abstract: A level shifter includes a level shifting unit suitable for changing a swing voltage level of an input signal from a first swing voltage level to a second swing voltage level based on a clock signal, a precharging unit suitable for precharging an output node of the level shifting unit based on the clock signal, and an output unit suitable for latching a signal of the output node having the second swing voltage level to output as an output signal.

Abstract: A level shifter comprising a first driver transistor for receiving an input signal. A gate-controlled transistor coupled to the first driver transistor. A second driver transistor coupled to the gate controlled transistor. An output coupled to the second driver transistor, wherein the gate-controlled transistor is for receiving a predetermined gate voltage when the output voltage exceeds a predetermined value.

Abstract: A glitch filter is disclosed herein. The glitch filter includes a high glitch filter circuit, a low glitch filter and a control circuit. The high glitch filter circuit is configured for generating a pull-up control signal in accordance with the input signal. The low glitch filter circuit is configured for generating a pull-down control signal in accordance with the input signal. The control circuit is configured for determining the logic level of the output of the glitch filter in accordance with the pull-up control signal and the pull-down control signal. A filtering method for filtering glitches is disclosed herein as well.

Abstract: According to an exemplary implementation, a level shifter includes a low voltage circuit and a high voltage circuit. The low voltage circuit is configured to provide a differential signal to the high voltage circuit through a capacitive isolation barrier. The high voltage circuit is configured to receive the differential signal from the low voltage circuit through the capacitive isolation barrier so as to level shift the differential signal from a first ground of the low voltage circuit to a second ground of the high voltage circuit. The high voltage circuit is further configured to provide a feedback signal to the low voltage circuit through the capacitive isolation barrier. The low voltage circuit can be configured to receive the feedback signal from the low voltage circuit between edges of the differential signal.

Abstract: Described herein is a distributed analog loop filter that can be employed in a phase locked loop or a delay locked loop. A circuit block of the distributed analog loop filter includes at least two parallel equivalent circuit elements. The parallel equivalent circuit elements each have an input line. The input lines for each of the parallel equivalent circuit elements are activated sequentially, one after the other. The parallel equivalent circuit elements have sequentially produced outputs that are also activated sequentially, one after another. The parallel equivalent circuit elements extend the tuning range of distributed analog filter while reducing noise associated with the distributed analog filter.

Abstract: Disclosed herein are an apparatus and method for controlling a lighting network. The apparatus for controlling lighting network includes a control device and a plurality of control gears. The control device generates and transfers commands to control lighting. The plurality of control gears receives the commands from the control device and control lighting. The control device assigns a right to use a lighting network to the control gears, and the control gears send information about a change in a lighting state or error details to the control device using the right to use a lighting network.

Abstract: A signal amplitude detection circuit includes a detector and a trimming algorithm module, and the detector having a preset baseline threshold reference value and an output terminal connected with the trimming algorithm module which is arranged for recording and decoding an output result of the detector to output an amplitude code value, and generating a control signal for controlling the baseline threshold reference value rise to a power supply level from a ground level or drop to the ground level from the power supply level, and the output result of the detector being “1” if a crossover occurs between the baseline threshold reference value and the detected signal; otherwise being “0”. The signal amplitude detection circuit detects the signal amplitude in a digital way, which has simpler structure, lower power consumption, reduced size of chips, and stable and accurate detection result without PVT drift.

Abstract: A mixer comprising a ladder having at least two resistances arranged in series and an input configured to receive an input signal and apply it across the ladder, said ladder including an output arrangement comprising at least three branches, a first branch branching from a first end of the ladder, a second branch branching from between the at least two resistances and a third branch branching from a second end of the ladder, opposite the first end, each branch including a switch for controlling a connection between its branch and an output.

Abstract: A tunable RF filter, comprising: an emitter follower stage (2); and a common emitter stage (4); the common emitter stage (4) providing feedback to the emitter follower stage (2). The common emitter stage (4) may comprise a first transistor (Ti) being the only transistor of the common emitter stage (4); and the emitter follower stage (2) may comprise a second transistor (T2) being the only transistor of the emitter follower stage (2). A further tunable RF filter provides improved linearity, comprising: an emitter follower stage (22); a joint common emitter and emitter follower stage (24); and a gain stage (26); a common emitter output of the joint common emitter and emitter follower stage (24) providing feedback to the emitter follower stage (22), and an emitter follower output of the joint common emitter and emitter follower stage (24) providing an input to the gain stage (26).

Abstract: A current-starved inverter circuit includes first and second current-mirror circuits, first and second transistors, a detector, and a current-booster. The first and second transistors receive a first source current and a first sink current from the first and second current-mirror circuits, respectively, and an input voltage signal, and generate an inverted input voltage signal (an output voltage signal). The detector generates a first detection signal when the output voltage signal exceeds a first threshold value and a second detection signal when the output voltage signal is less than a second threshold value. The current-booster, which is connected to the detector, receives the first and second detection signals and provides a second source current and a second sink current to the first and second transistors to pull-up and pull-down a voltage level of the output voltage signal, respectively.

Abstract: An electronic circuit apparatus for compensating for a process variation of a resistor in an electronic circuit is provided. The electronic circuit includes a detecting part for generating a tune voltage corresponding to a process variation value of the at least one resistor, and a compensating part for compensating for a process variation of the at least one resistor using the tune voltage.

Abstract: In accordance with an example embodiment, there is disclosed herein a LED PAPI (10) with condensation protection. The condensation protection may suitably comprise passive components, such as gaskets and seals (26, 36) and a desiccant (48), and/or active components, such as a defroster (39) and/or a heater (50).

Abstract: A vehicle lamp includes a light source (LED) 2, a solenoid-type actuator 6, and a lamp control device LC. The light source 2 lights up when a current flows therethrough. The actuator 6 controls a light distribution of light that is illuminated from the light source 2. The lamp control device LC controls lighting-up of the light source 2 and driving of the actuator 6. The lamp control device LC includes a current control device 10 and an actuator control device 20. The current control device 10 outputs a constant current. The actuator control device 20 connects the actuator 6 to the light source 2 in series based on a predetermined signal so that the constant current, which is output from the current control device 10, flows through the light source 2 and the actuator 6.

Abstract: A filtering circuit includes a clock selection unit configured to transfer a first clock or a second clock having a frequency lower than the first clock as an operating clock in response to a frequence signal, and a filter configured to filter an input signal and generate a filtered signal in synchronization with the operating clock.

Abstract: A resonator is connected to a first plane which is one of a power plane and a ground plane, wherein the power plane and the ground plane are apart from each other in an up-down direction. The resonator comprises a connecting portion and a body portion. The connecting portion is connected to the first plane. The connecting portion extends in the up-down direction beyond a second plane, which is a remaining one of the power plane and the ground plane, while not being in electrical contact with the second plane. The body portion is connected to the connecting portion while not being in contact with the second plane. The body portion is arranged so that the second plane is located between the body portion and the first plane in the up-down direction.

Abstract: A metallic waveguide is mounted on a multilayer substrate. The metallic waveguide has an open end formed by a top, bottom and sides configured to receive a core member of a dielectric waveguide, and an opposite tapered end formed by declining the top of the metallic waveguide past the bottom of the metallic waveguide and down to contact the multilayer substrate. A pinnacle of the tapered end is coupled to the ground plane element, and the bottom side of the metallic waveguide is in contact with the multiplayer substrate and coupled to the microstrip line.

Abstract: An asynchronous level shifter electronic circuit including: a transmitter, which can be coupled to a first voltage and generates a communication signal; a receiver, which can be coupled to a second voltage; and a capacitive coupling stage, which receives the communication signal and supplies a corresponding filtered signal to the receiver. The receiver includes: a threshold device, which has an input terminal and an output terminal and switches an electrical quantity on the output terminal between a first value and a second value, as a function of corresponding transitions through a threshold of a first intermediate signal present on the input terminal, to generate a second intermediate signal; and a biasing circuit, which generates the first intermediate signal to have a d.c. component, which is a function of the second intermediate signal, and superposed on which is a variable component, which is a function of the filtered signal.

Abstract: A power-supply device has a first power supply circuit adapted to generate from an input voltage a first output voltage and a second power supply circuit adapted to generate from the first output voltage a second output voltage. The second power supply circuit monitors the first output voltage to check if it is higher than a first threshold voltage, and also monitors the first power-supply circuit to check if it has started operation for generating the first output voltage, so that the second power supply circuit stays on stand-by, even when the first output voltage is higher than the first threshold voltage, until the first power supply circuit starts operation for generating the first output voltage.

Abstract: A harmonic rejection mixer is disclosed that is capable of supporting wideband reception without any increase in circuit area. In this apparatus, transistors convert an RF signal to currents. Transistors perform frequency conversion based on the currents from the transistors and local oscillation signals. Transistors distribute the currents from the transistors to all transistors or some transistors based on a predetermined ratio. A load adds up the currents from the transistors and converts the resultant current to a voltage.

Abstract: An output circuit, between a first power supply terminal and a second power supply terminal, receives a first logic signal that switches between a first logic state based on a voltage at the first power supply terminal and a second logic state based on a voltage at the second power supply terminal and provides a second logic signal, complementary to the first logic signal. A level translator is in a second power supply domain configured to have a second voltage differential between a third power supply terminal and a fourth power supply terminal, wherein the second voltage differential is greater than the first voltage differential. The level translator is designed so that it may be implemented using a subset of the transistors that have the shortest channel length and narrowest channel width.