Patents Examined by Dinh T. Le
  • Patent number: 10897247
    Abstract: A description is given below of an intelligent semiconductor switch and also a method for operating an intelligent semiconductor switch integrated in a chip package. In accordance with one exemplary embodiment, the method comprises, in a first mode, in which a state control signal having a first logic level is received at a control terminal of the chip package, driving a first and a second semiconductor switch of a half-bridge in accordance with an input signal received at an input terminal of the chip package. In a second mode, in which a state control signal having a second logic level is received at the control terminal of the chip package, the method comprises setting an operating parameter depending on a pulse pastern of the input signal received at the input terminal.
    Type: Grant
    Filed: January 28, 2020
    Date of Patent: January 19, 2021
    Assignee: Infineon Technologies AG
    Inventors: Carlos Joao Marques Martins, Markus Bader
  • Patent number: 10884450
    Abstract: One embodiment includes a clock distribution system. The system includes at least one resonator spine that propagates a clock signal and at least one resonator rib conductively coupled to the at least one resonator spine and being arranged as a standing wave resonator. At least one of the at least one resonator rib has a thickness that varies along a length of the respective one of the at least one resonator rib. The system also includes at least one transformer-coupling line. Each of the at least one transformer-coupling line can be conductively coupled to an associated circuit and being inductively coupled to the at least one resonator rib to inductively generate a clock current corresponding to the clock signal to provide functions for the associated circuit.
    Type: Grant
    Filed: March 6, 2018
    Date of Patent: January 5, 2021
    Assignee: NORTHROP GRUMMAN SYSTEMS CORPORATION
    Inventors: Joshua A. Strong, Max E. Nielsen
  • Patent number: 10886690
    Abstract: The present invention provides systems and methods for optical frequency comb generation with self-generated optical harmonics in mode-locked lasers for detecting the carrier envelope offset frequency. The mode-locked laser outputs an optical frequency comb and a harmonic output. The harmonic output provides an optical heterodyne resulting in a detectable beat note. A carrier envelope offset frequency detector detects the beat note and generates an optical frequency comb signal. The signal can be used to stabilize the optical frequency comb output.
    Type: Grant
    Filed: January 5, 2018
    Date of Patent: January 5, 2021
    Assignee: IPG PHOTONICS CORPORATION
    Inventor: Sergey Vasilyev
  • Patent number: 10886841
    Abstract: A hybrid switched capacitor power converter for high-power applications is provided. The converter has a transistor-switched input-stage boost converter followed by a capacitor-and-diode ladder circuit. The converter is adapted to produce an output voltage of at least 5 kV at a power level of at least 0.5 kW. The ladder circuit includes one or more multi-stage rails.
    Type: Grant
    Filed: April 15, 2019
    Date of Patent: January 5, 2021
    Assignee: National Technology & Engineering Solutions of Sandia, LLC
    Inventors: Robert W. Brocato, Jason C. Neely, Lee Joshua Rashkin, Jarod James Delhotal, Jack David Flicker, Robert Kaplar, Joshua Stewart, James Richards
  • Patent number: 10879878
    Abstract: Embodiments of the invention provide for a drop-in solid-state relay replacement for current standard relays. The drop-in solid-state relay may comprise receiving an input power and actuating at least one transistor to provide power to operational equipment. In some embodiments, an optical isolator may be disposed at an output driver stage of the relay circuit to provide electrical isolation between the input stage and the output stage. The drop-in solid-state relay may provide low input voltage, low heat, no noise, and not produce fly-back.
    Type: Grant
    Filed: December 16, 2019
    Date of Patent: December 29, 2020
    Assignee: Altec Industries, Inc.
    Inventor: Tyler Hinnen
  • Patent number: 10879890
    Abstract: A cascade complementary source follower and a controlling circuit are provided. The source follower circuit includes: a source follower circuit including at least two MOS transistors, and a feedback circuit configured to clamp a voltage on a MOS transistor that provides an output voltage in the source follower circuit and to change a gate-source voltage of the MOS transistor by adjusting a bias current supplied to the MOS transistor, so that an output voltage can precisely follow an input voltage.
    Type: Grant
    Filed: January 21, 2020
    Date of Patent: December 29, 2020
    Assignee: LONTIUM SEMICONDUCTOR CORPORATION
    Inventors: Cheng Tao, Xiangyu Ji, Yu Chen, Haiyan Wei, Yanan Zhang, Jiaxi Fu
  • Patent number: 10873323
    Abstract: A low-power transmitter for transmitting digital signals from an integrated chip is described herein. The transmitter includes a voltage-mode transmitter driver comprised of a plurality of driver slices, which includes an up-cell having a first resistor and a first transistor, and a down-cell having a second resistor, a second transistor, and a third transistor. A calibration circuit drives a replica circuit to a desired impedance by adjusting a first gate voltage applied to the first transistor of the replica of the up-cell and adjusting a second gate voltage applied to the third transistor of the replica of the down-cell. The calibrated first gate voltage is applied to the first transistor and to the second transistor of each of the plurality of driver slices and the calibrated second gate voltage is applied to the third transistor of each of the plurality of driver slices.
    Type: Grant
    Filed: January 31, 2020
    Date of Patent: December 22, 2020
    Assignee: Marvell Asia Pte, Ltd.
    Inventors: Fei Guo, Yihui Li, Hong Xue, Xin Ma, Hui Wang
  • Patent number: 10873258
    Abstract: A semiconductor device includes a charge pump circuit suitable for generate an output voltage by pumping an input voltage according to first and second main clocks; a voltage detection circuit suitable for generating a comparison signal by comparing the output voltage with a reference voltage; and a driving control circuit suitable for generating the first and second main clocks according to first and second external clocks during an activation time period of the comparison signal while controlling a transition sequence such that the second main clock transitions after the first main clock transitions.
    Type: Grant
    Filed: January 2, 2020
    Date of Patent: December 22, 2020
    Assignee: SK hynix Inc.
    Inventors: Jong-Seok Kim, Geon-Hwi Lee
  • Patent number: 10871796
    Abstract: In some examples, a system includes a clock source, a clock distribution network, and a plurality of clock generators. The clock source is configured to generate a global clocking signal. The clock distribution network is configured to fan out the global clocking signal to a plurality of loads. The plurality of clock generators is configured to receive the global clocking signal through the clock distribution network. Each clock generator of the plurality of clock generators is configured to generate a related clocking signal to the global clocking signal from the received global clocking signal. Each clock generator of the plurality of clock generators maybe configured to supply the global clocking signal or the related clocking signal to its respective load of the plurality of loads.
    Type: Grant
    Filed: August 6, 2019
    Date of Patent: December 22, 2020
    Assignee: XILINX, INC.
    Inventors: Brian C. Gaide, Chiao K. Hwang, Guoqing Ning, Richard W. Swanson, Wayne E. Wennekamp
  • Patent number: 10868524
    Abstract: A semiconductor circuit and a semiconductor circuit layout system are provided. The semiconductor circuit includes a clock inverter which inverts a clock signal and outputs an inverted clock signal where the clock inverter is laid out between a second master latch main circuit configured to latch signals of a first node and a fourth node based on the clock signal and the inverted clock signal, respectively, and a second slave latch main circuit configured to latch signals of a second node and a fifth node based on the clock signal and the inverted clock signal, respectively.
    Type: Grant
    Filed: August 8, 2019
    Date of Patent: December 15, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Young O Lee, Doo Seok Yoon, Min Su Kim
  • Patent number: 10868520
    Abstract: A radio frequency switch includes a control buffer circuit to generate a first gate voltage and a first body voltage; and a switching circuit to switch at least one signal path in response to the first gate voltage and the first body voltage. The control buffer circuit includes an off voltage detection circuit to detect whether the off voltage is a negative voltage or a ground voltage and output a voltage detection signal, a first gate buffer circuit to output a first gate voltage having a voltage level based on the voltage detection signal and the band selection signal, and a first body buffer circuit to output a first body voltage having a voltage level based on the voltage detection signal, the band selection signal, and the mode signal.
    Type: Grant
    Filed: February 1, 2019
    Date of Patent: December 15, 2020
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Byeong Hak Jo, Jeong Hoon Kim, Hyun Paek
  • Patent number: 10862466
    Abstract: A circuit controls a dynamic time constant to remove DC offset from a received optical data signal. The circuit has a first capacitor coupled between a first terminal and a second terminal. A first resistance network is coupled between the second terminal and a reference voltage. A control circuit has a first output coupled to a control input of the first resistance network. The control circuit monotonically increases an effective resistance of the first resistance network to increase the dynamic time constant. The first resistance network has a resistor coupled to the second terminal, and a transistor with a first conduction terminal coupled to the resistor, a second conduction terminal coupled to the reference voltage, and a control terminal coupled to the first output of the control circuit. The first capacitor has a variable capacitance. The monotonic increase in the dynamic time constant can be linear or non-linear.
    Type: Grant
    Filed: February 9, 2019
    Date of Patent: December 8, 2020
    Assignee: Semtech Corporation
    Inventors: Miguel Valencia, Nikolaos Vogiatzis
  • Patent number: 10854379
    Abstract: Provided is a wireless power transfer antenna core. In the wireless power transfer antenna core according to an exemplary embodiment of the present invention, a conductive member configured to serve as an antenna for transmitting or receiving wireless power is wound multiple times along a longitudinal direction. The wireless power transfer antenna core is made of a magnetic body and comprises: a first portion having a first cross-sectional area; and a second portion extending with a predetermined length from an end of the first portion and second cross-sectional area that is relatively larger than the first cross-sectional area, wherein the conductive member is wound multiple times on the first portion.
    Type: Grant
    Filed: September 28, 2017
    Date of Patent: December 1, 2020
    Assignee: AMOSENSE CO., LTD.
    Inventors: Won San Na, Byoung Su Jin, Do Sick Kim, Bo Hyeon Han
  • Patent number: 10855170
    Abstract: A power management integrated circuit (PMIC) is provided for extracting power from an energy harvester. The PMIC includes a voltage converter to convert an input power at a voltage Vin into an output power at an output voltage Vout_VC. The voltage converter includes, in addition to a main voltage converter circuit, a cold-start circuit for starting the voltage converter from an OFF state. The PMIC further includes an input terminal for receiving a voltage VEN-CS proportional to the converter input voltage Vin and a voltage comparator for comparing the voltage VEN-CS with a reference voltage Vref. A controller enables the cold-start circuit when VEN-CS?Vref.
    Type: Grant
    Filed: June 21, 2018
    Date of Patent: December 1, 2020
    Assignee: E-PEAS S.A.
    Inventors: Julien De Vos, Geoffroy Gosset, Cedric Hocquet
  • Patent number: 10855274
    Abstract: A semiconductor device includes: a first IGBT and a second IGBT to constitute an inverter; a primary-side IC chip to output an electrical signal responsive to an input signal; a first secondary-side IC chip to drive the first IGBT based on the electrical signal; and a second secondary-side IC chip to drive the second IGBT based on the electrical signal. The primary-side IC chip includes insulating elements electrically insulated from the first secondary-side IC chip and the second secondary-side IC chip. The first secondary-side IC chip is stacked on the first IGBT. The second secondary-side IC chip is stacked on the second IGBT.
    Type: Grant
    Filed: January 13, 2020
    Date of Patent: December 1, 2020
    Assignee: Mitsubishi Electric Corporation
    Inventor: Motoki Imanishi
  • Patent number: 10845832
    Abstract: A voltage-to-current converter can be configured to generate a current based on an input voltage and for part of the time use the generated current as the output current of the voltage-to-current converter, and for part of the time use the generated current as a current source for the operation of the voltage-to-current converter. This arrangement can reduce the need for high performance current mirror circuits within the voltage-to-current converter, thereby reducing the cost and complexity of the voltage-to-current converter and improving precision and accuracy.
    Type: Grant
    Filed: September 5, 2019
    Date of Patent: November 24, 2020
    Assignee: Analog Devices International Unlimited Company
    Inventor: Jonathan Ephraim David Hurwitz
  • Patent number: 10847874
    Abstract: Disclosed is an antenna module for a vehicle, which can perform wireless power transmission for a portable terminal equipped with a magnetic resonance wireless power transmission function and a portable terminal equipped with a magnetic induction wireless power transmission function in one module. The disclosed antenna module for the vehicle stacks a first antenna unit having a first antenna that is an antenna for the magnetic resonance wireless power transmission and near field communication on one surface of a base sheet, and a second antenna unit having a second antenna that is an antenna for the magnetic induction wireless power transmission on one surface of the first antenna unit; and the second antenna is partially overlapped with the first antenna.
    Type: Grant
    Filed: October 21, 2016
    Date of Patent: November 24, 2020
    Assignee: AMOTECH CO., LTD.
    Inventors: Jae-Il Park, Hyung-Il Baek, Kyung-Hyun Ryu
  • Patent number: 10847994
    Abstract: A system includes a direct current uninterruptible power supply (DC UPS) that receives an alternating current (AC) power input and provides a first DC power output. The system also includes a power distribution unit (PDU). The PDU receives the first DC power output from the DC UPS. The PDU converts the first DC power output into a second DC power output that supplies power to at least one component of information technology equipment (ITE) via a DC mating connector.
    Type: Grant
    Filed: March 15, 2019
    Date of Patent: November 24, 2020
    Assignee: SEAGATE TECHNOLOGY LLC
    Inventors: Hemant Mohan, Deepak Nayak, Rajesh Maruti Bhagwat
  • Patent number: 10839751
    Abstract: Embodiments of the present application provide a scan driving circuit, a scan driver and a display device. The scan driving circuit includes a first control module, a second control module and an output module. The output module includes a first switching unit, a second switching unit and a scan driving signal output end. The first switching unit and the second switching unit are connected in parallel and are connected with the scan driving signal output end. A port of the first switching unit is away from the scan driving signal output end to receive a second clock signal. A port of the second switching unit is away from the scan driving signal output end to receive a first reference signal. A function of outputting the scan driving signal by using fewer components is realized with the scan driving circuit according to the embodiments of the present application.
    Type: Grant
    Filed: February 1, 2019
    Date of Patent: November 17, 2020
    Assignee: KunShan Go-Visionox Opto-Electronics Co., Ltd.
    Inventors: Jianlong Wu, Siming Hu, Hui Zhu
  • Patent number: 10833665
    Abstract: A multi-phase clock generator circuit includes a phase reference generator circuit configured to generate a phase reference signal in response to a phase selection signal and a peak ramp signal. A phase error correction circuit is configured to provide an error signal based on a synchronization clock signal and a multi-phase clock signal. The error signal is applied to the phase reference signal to correct for phase errors in the multi-phase clock signal. A comparator is configured to compare a ramp signal and the phase reference signal to produce the multi-phase clock signal.
    Type: Grant
    Filed: August 26, 2019
    Date of Patent: November 10, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventor: Jianfeng Jiang