Abstract: In a layered coding approach, a code configuration parameter of a polar code is determined, and encoding graph parameters are determined based on the determined code configuration parameter. The encoding graph parameters identify inputs for one or more kernel operations in each of multiple encoding layers. Information symbols are encoded by applying the one or more kernel operations to the inputs identified in each encoding layer in accordance with the determined encoding graph parameters.

Abstract: In one embodiment, linked-list interlineation of data in accordance with the present description includes inserting a subsequent set of data in a linked-list data structure within an initial data structure. The linked-list data structure includes a sequence of linked-list entries interspersed with the initial data of the initial data structure. To insert the subsequent data, a pattern of data within the initial data structure is replaced with data of the subsequent set of data in a sequence of linked-list entries of the linked-list data structure. Other aspects are described herein.

Abstract: An error correction circuit includes a syndrome calculator suitable for generating syndromes from an “n”-bit codeword for a single unit of time, an error location polynomial calculator suitable for generating error location polynomial coefficients based on the syndromes provided for the single unit of time, an error location calculator suitable for calculating error locations based on the error location polynomial coefficients for the single unit of time, and an error corrector suitable for correcting errors of the codeword based on the error locations for the single unit of time. The error correction circuit operates in a pipelining manner.

Abstract: A cache memory has a data cache to store data per cache line, a tag to store address information of the data to be stored in the data cache, a cache controller to determine whether an address by an access request of a processor meets the address information stored in the tag and to control access to the data cache and the tag, and a write period controller to control a period required for writing data in the data cache based on at least one of an occurrence frequency of read errors to data stored in the data cache and a degree of reduction in performance of the processor due to delay in reading the data stored in the data cache.

Abstract: Address verification on a bus, the bus connecting a plurality of receiving bus nodes and one or more sending bus nodes, the bus providing communication among the bus nodes, including: receiving, by a receiving bus node over the bus, a parity signal and an address signal, the address signal identifying an address of a target receiving bus node; determining, by the receiving bus node, whether the address of the target receiving bus node matches an address of the receiving bus node; responsive to determining that the address of the target receiving bus node matches the address of the receiving bus node, determining, by the receiving bus node, whether the parity signal is an expected parity signal; and responsive to determining that the parity signal is not the expected parity signal, suppressing, by the receiving bus node, an acknowledgment of receipt of the address signal.

Abstract: The invention relates to an electronic circuit (10) having one or more latch scan chains (12), the electronic circuit (10) comprising (i) a built-in test structure (14); (ii) generation means (16) for simultaneously generating scan-in data for each of said scan chains (12); (iii) interception means (18) for simultaneously intercepting test lines (20) of said scan chains (12), said test lines (20) comprising scan-in lines (22) and/or control lines (24). Said interception means (18) are responsive to said generation means (16) in order to simultaneously feed the generated scan-in data into each of said scan chains (12) for initializing the electronic circuit (10). The invention further relates to a method for initializing an electronic circuit (10), as well as a data processing system (210) for initializing an electronic circuit (10).

Abstract: A method begins by a dispersed storage (DS) processing module segmenting a data partition into a plurality of data segments. For a data segment of the plurality of data segments, the method continues with the DS processing module dividing the data segment into a set of data sub-segments and generating a set of sub keys for the set of data sub-segments based on a master key. The method continues with the DS processing module encrypting the set of data sub-segments using the set of sub keys to produce a set of encrypted data sub-segments and aggregating the set of encrypted data sub-segments into encrypted data. The method continues with the DS processing module generating a masked key based on the encrypted data and the master key and combining the encrypted data and the masked key to produce an encrypted data segment.

Abstract: A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 64800 and a code rate of 2/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for 256-symbol mapping.

Abstract: An integrated circuit device includes a first partition and a second partition. The integrated circuit device also includes a Joint Test Action Group (JTAG) system that controls at least a portion of the integrated circuit device via logic signals. The JTAG system includes a JTAG interface that receives logic signals and a first JTAG hub instantiated in the first partition communicatively coupled to the JTAG interface. The integrated circuit device further includes a second JTAG hub instantiated in the second partition communicatively coupled to the first JTAG hub via a bridge.

Abstract: A method includes dispersed storage error encoding a data object into a plurality of sets of encoded data slices. The method further includes determining a local slice storage number, a local area network (LAN) slice storage number, and a wide area network (WAN) slice storage number, wherein a sum of the local slice number, the LAN slice storage number, and the WAN slice storage number equals the pillar width number. For at least some sets of encoded data slices, the method further includes sending the local slice storage number of encoded data slices to the local slice storage number of local memory devices; sending the LAN slice storage number of encoded data slices to the LAN slice storage number of LAN storage units of the DSN; and sending the WAN slice storage number of encoded data slices to the WAN slice storage number of WAN storage units of the DSN.

Abstract: A microcontroller includes a data memory configured to store test signal data. The microcontroller further includes a signal generator configured to process the test signal data in order to provide at least one test signal. The microcontroller also includes a circuit under test configured to process the test signal. The test signal data includes at least one pattern snippet and an associated pattern descriptor. The pattern snippet includes data concerning a content of a part of the test signal. The associated pattern descriptor includes data concerning a pattern formed by the pattern snippet within the test signal.

Abstract: A method includes: defining a plurality of clock architecture attributes for a plurality of clock domains to be tested; assigning each one of the plurality of clock domains to a first test group; and refining the assignment of each one of the plurality of clock domains based on the plurality of clock architecture attributes until each of the plurality of clock domains is grouped into a current test group.

Abstract: Methods and apparatuses are provided for operating a list Viterbi decoder. A path metric difference (PMD) threshold is set based on an input signal level and a PMD limit value. Decoding is performed by using the PMD threshold. Performing the decoding includes determining a PMD of a best path, comparing the determined PMD and the PMD threshold, and declaring a decoding failure and ending performing of the decoding, if the PMD is greater than or equal to the PMD threshold.

Abstract: Disclosed are a method and a device for recovering an error without the retransmission of a data frame in a wireless LAN. The method for recovering an error in a wireless LAN may comprise the steps in which: a sender STA transmits a data frame to a receiver STA; if the sender STA does not receive a block ACK frame of the data frame from the receiver STA, the sender STA determines the reason for the non-reception of the data frame; if the sender STA determines that the reason for the non-reception of the data frame is the failure of transmission of the block ACK frame after the receiver STA receives the data frame, the sender STA transmits a PBAR data frame to the receiver STA; and the sender STA receives a PBAR block ACK frame from the receiver STA as a response to the PBAR data frame.

Abstract: A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 64800 and a code rate of 5/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for 4096-symbol mapping.

Abstract: An embodiment may involve receiving a chunk and a chunk index, where the chunk contains packets captured by a network interface unit and the chunk index contains timestamps of first and last packets within the chunk. The chunk may be stored in a first ring buffer of a first memory and the chunk index may be stored in an index buffer of the first memory. A first processor may allocate an entry in an I/O queue of a second memory and an entry in a chunk processing queue of the first memory. The first processor may read the chunk processing queue to identify and copy the chunk from the first ring buffer to a location in a second ring buffer of the second memory, the location associated with the entry in the I/O queue. A second processor may instruct a controller to write the chunk to a non-volatile memory unit.

Abstract: A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 64800 and a code rate of 4/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for 256-symbol mapping.

Abstract: A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 16200 and a code rate of 4/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for 16-symbol mapping.

Abstract: A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 64800 and a code rate of 3/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for 1024-symbol mapping.

Abstract: A low density parity check (LDPC) encoder, an LDPC decoder, and an LDPC encoding method are disclosed. The LDPC encoder includes first memory, second memory, and a processor. The first memory stores an LDPC codeword having a length of 16200 and a code rate of 2/15. The second memory is initialized to 0. The processor generates the LDPC codeword corresponding to information bits by performing accumulation with respect to the second memory using a sequence corresponding to a parity check matrix (PCM).