Abstract: An error detection circuit on a semiconductor chip detects whether soft errors have affected flip-flop implemented registers on the semiconductor chip. A signature of these flip-flop implemented registers on the semiconductor chip is periodically captured. The signature allows for the integrity of the flip-flop implemented registers to be constantly monitored. A soft error occurring on any of the flip-flop implemented registers can be immediately detected. In response to the detection, an interrupt is raised to notify software to take action.

Abstract: In a method of circuit yield analysis, the method includes: detecting a plurality of failed samples respectively located at a plurality of failure regions in a multi-dimensional parametric space; clustering the failed samples to identify the failure regions; filtering features of the failed samples to determine a parameter component that is a non-principal component in affecting circuit yield; applying a dimensional reduction method on a dimension corresponding to the parameter component; and constructing a final importance sampling (IS) distribution function using a mixed Gaussian (mGaussian) function corresponding to all of the failure regions containing a rare failure event.

Abstract: Technology for correcting memory read errors including a preprocessing majority logic decode based on a plurality of identity structures of a parity check matrix, before ECC decoding using the parity check matrix, to estimate a set of erased or punctured bits of a codeword.

Abstract: Providing non-destructive recirculation test support in a device under test includes determining an initial latch allocation of a plurality of latches to form a plurality of self-test chains for the device under test. An optimized latch allocation to the self-test chains is determined based on a plurality of physical and logical grouping constraints. One or more of the latches are adjusted and reassigned between one or more of the self-test chains based on the optimized latch allocation. A recirculating feedback is coupled from an output of at least one of the self-test chains to a recirculation selector. A test input source is coupled to the recirculation selector, where the recirculation selector is operable to select between providing the test input source or the recirculating feedback to an input of the at least one of the self-test chains.

Abstract: A computer-implemented method includes receiving probability distribution function (PDF) data corresponding to bit-error-rate (BER) data for each of a plurality of data blocks within a qualified set of NVRAMS, collecting non-exhaustive bit-error-rate data for each of the data blocks on a tested NVRAM to produce non-exhaustive test data for each of the data blocks, determining a plurality of stable data blocks on the tested NVRAM based on the non-exhaustive test data and the probability distribution function data for each of the data blocks, determining, from the non-exhaustive test data, an inferior data block for the stable data blocks on the tested NVRAM, collecting exhaustive bit-error-rate data on the inferior data block to produce exhaustive test data for the tested NVRAM, and routing the tested NVRAM according to the exhaustive test data. A corresponding computer program product and computer system are also disclosed herein.

Abstract: Methods and apparatus disclosed herein may be used to establish framing more efficiently in communication protocols with block-coded forward error correction. Such protocols generally involve the check of different bit-alignments searching for positions that yield zero syndromes. The search can be undesirably slow, particularly in the presence of received errors. The presently-disclosed bit-alignment testing technique reduces this search time by checking the syndrome at each data word as if that data word was the last of a code. In other words, the word positions are effectively checked without a prior assumption as to which words are the first and last of the code. This reduces the task to the number of different bit-alignments possible within a single data word, rather than the number of bit-alignments possible in a complete FEC code. In one implementation, the lock time is reduced by approximately 50 times when compared to a straightforward solution.

Abstract: A communications device includes: a processor, configured to determine a quantity of first idle channels; and a transmitter, configured to send data to a receiving end on each of the first idle channels; wherein the processor is further configured to: determine whether the data is to be resent; and if the data is to be resent, cause the transmitter to resend the data; and continue to determine whether the data is to be resent and, if the data is to be resent, re-determine the quantity of first idle channels and cause the transmitter to resend the data.

Abstract: Scale out data protection with erasure coding is presented herein. Based on an initial number of storage devices determined to have been included in an initial stage of a data storage cluster, an initial protection scheme for the initial stage can determine first coding fragment(s) for data stored within the data storage cluster to facilitate a first recovery, from the initial stage, of the data using the first coding fragment(s). Further, in response to a defined number of additional storage devices being determined to have been added to the data storage cluster to generate a modified data storage cluster, the initial protection scheme can be modified to obtain a modified protection scheme that can determine, for the modified data storage cluster, second coding fragment(s) for the data to facilitate a second recovery of the data using the first coding fragment(s) and the second coding fragment(s).

Abstract: A sensor system is configured to communicate at least partially protected sensor data over a communication interface. The sensor system includes a sensor element and a communication interface communicatively coupled to the sensor element. The sensor element is configured to provide sensor data in the digital domain. The communication interface is configured to generate a data package for transmission over the communication interface from the sensor data. The data package includes a data grouping comprising one or more nibbles related to the sensor data. The data package further includes a nibble indicia based on at least a portion of selected nibbles within the data grouping.

Abstract: One embodiment of the present invention capable of decommissioning a defective non-volatile memory (“NVM”) page in a block is disclosed. A process able to logically decommission a defective page is able to detect defective or bad pages while executing a write operation writing information to one or more NVM page in a NVM block. For example, after examining operation status after completion of the write operation, the NVM page is identified as a defective page if the operation status fails to meet a set of predefined conditions under a normal write operation. Upon marking a location of a page status table to indicate the NVM page as defective page, the page status table containing the page defective information associated with the NVM page is stored at a predefined page in the NVM block.

Abstract: The disclosure describes a novel method and apparatus for improving silicon interposers to include test circuitry for testing stacked die mounted on the interposer. The improvement allows for the stacked die to be selectively tested by an external tester or by the test circuitry included in the interposer.

Abstract: A communication system is a communication system that includes first and second information processing devices. The first information processing device performs control such that a signal (which is a signal having backward compatibility) serving as an index by which the second information processing device receiving a frame stops the reception of the frame is transmitted to the second information processing device. The second information processing device performs control such that the reception of the frame is stopped based on the signal (which is a signal having backward compatibility) serving as an index by which reception of the frame is stopped when the frame transmitted from the first information processing device is received.

Abstract: A signature-enabled Polar code encoder and decoder are provided. Signature bits are inserted in some unreliable bit positions. Different signature bits are inserted for different receivers. For a given codeword, only the receiver with knowledge of the signature can decode the codeword. Cyclic redundancy check (CRC) bits may be included in the input vector to assist in decoding.

Abstract: Apparatuses and methods for temperature related error management are described. One or more apparatuses for temperature related error management can include an array of memory cells and a write temperature indicator appended to at least one predetermined number of bytes of the stored data in the array of memory cells. The apparatuses can include a controller configured to determine a numerical temperature difference between the write temperature indicator and a read temperature indicator and determine, from stored operations, an error management operation for the stored data based, at least in part, on comparison of the numerical temperature difference to a temperature difference threshold.

Abstract: Embodiments of the present application relate to a method for implementing Turbo equalization compensation. The equalizer divides a first data block into n data segments, where D bits in two adjacent data segments in the n data segments overlap, performs recursive processing on each data segment in the n data segments, before the recursive processing, merges the n data segments to obtain a second data block; and performs iterative decoding on the second data block, to output a third data block, where data lengths of the first data block, the second data block, and the third data block are all 1/T of a code length of a LDPC convolutional code.

Abstract: A memory chip architecture includes a plurality of test pads, a plurality of interface pads, a function block and an embedded test block. The function block is coupled to the interface pads. The embedded test block is coupled to the test pads. The embedded test block is connected to an access port physical layer (PHY) through the interface pads. The interface pads are disposed between the function block and the embedded test block. The embedded test block is arranged for generating at least one test pattern as a test signal, and outputting the test signal to the function block through the interface pads to test the function block.

Abstract: In described examples, an apparatus includes: a set of control registers containing control bits for controlling circuitry coupled to receive register write enable signals and to receive input data; a memory for storing data corresponding to the control bits coupled to receive an address and a memory write enable signal; decode circuitry coupled to output the register write enable signals; a data output bus coupled to receive data from the memory but free from connections to the control registers; and a controller coupled to receive an address, coupled to output the address on an internal address bus, coupled to output a register write enable signal, and coupled to output the memory write enable signal, configured to cause data to be written to a selected control register corresponding to the address received, and to cause the data to be contemporaneously stored at a memory location corresponding to the address received.

Abstract: A distributed data storage system breaks data into n slices and k checksums using at least one matrix-based erasure code based on matrices with invertible submatrices, stores the slices and checksums on a plurality of storage elements, retrieves the slices from the storage elements, and, when slices have been lost or corrupted, retrieves the checksums from the storage elements and restores the data using the at least one matrix-based erasure code and the checksums. In a method for ensuring restoration and integrity of data in computer-related applications, data is broken into n pieces, k checksums are calculated using at least one matrix-based erasure code based on matrices with invertible submatrices, and the n data pieces and k checksums are stored on n+k storage elements or transmitted over a network.

Abstract: Disclosed are a method and a device for recovering an error without the retransmission of a data frame in a wireless LAN. The method for recovering an error in a wireless LAN may comprise the steps in which: a sender STA transmits a data frame to a receiver STA; if the sender STA does not receive a block ACK frame of the data frame from the receiver STA, the sender STA determines the reason for the non-reception of the data frame; if the sender STA determines that the reason for the non-reception of the data frame is the failure of transmission of the block ACK frame after the receiver STA receives the data frame, the sender STA transmits a PBAR data frame to the receiver STA; and the sender STA receives a PBAR block ACK frame from the receiver STA as a response to the PBAR data frame.

Abstract: A system-in-package module with memory includes a non-memory chip, a substrate, and a memory chip. The non-memory chip has a first portion and a second portion. The substrate has a window and the substrate is electrically connected to the second portion of the non-memory chip. The memory chip is placed into the window of the substrate to electrically connect the first portion of the non-memory chip, and there is no direct metal connection between the memory chip and the substrate.