Abstract: A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 64800 and a code rate of 3/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for 16-symbol mapping.

Abstract: A computing system includes: a data block including data pages and each of the data pages includes data sectors and each of the data sectors include sector data and a sector redundancy; a storage engine, coupled to the data block, configured to: apply a first protection across the data pages, apply a second protection across the data sectors, and correct at least one of the data sectors when a sector correction with the sector redundancy failed with the first protection and the second protection.

Abstract: A memory-specific implementation of a test and characterization vehicle utilizes a design layout that is a modified version of the product mask. Specific routing is used to modify the product mask in order to facilitate memory cell characterization. This approach can be applied to any memory architecture with word-line and bit-line perpendicular or substantially perpendicular to each other, including but not limited to, volatile memories such as Static Random Access Memory (SRAM), Dynamic RAM (DRAM), non-volatile memory such as NAND Flash (including three-dimensional NAND Flash), NOR Flash, Phase-change RAM (PRAM), Ferroelectric RAM (FeRAM), Correlated electron RAM (CeRAM), Magnetic RAM (MRAM), Resistive RAM (RRAM), XPoint memory and the like.

Abstract: A Low-Density Parity-Check (LDPC) decoder and a method for LDPC decoding are provided. The LDPC decoder receives a soft-decision input codeword block in which the probability of a bit being a “0” or a “1” is represented as a log-likelihood ratio (LLR). During LDPC decoding, a sequence of hardware logic units iteratively updates the soft-decision input codeword block until a valid codeword is found or a maximum number of decoding iterations is reached. Each hardware logic unit comprises a check node (CN) update logic unit and a variable node (VN) update logic unit. The CN update logic units are coupled via a closed CN path, and the VN update logic units are coupled via a closed VN path. Aspects of this LDPC decoder alleviate the global routing and energy efficiency challenges of traditional LDPC decoders, to enable multi-rate, multi-Gb/s decoding without compromising error correction performance in next-generation systems and future CMOS technology nodes.

Abstract: Non-volatile memory block management. A method according to one embodiment includes calculating an error count margin threshold for each of the at least some non-volatile memory blocks of a plurality of non-volatile memory blocks. A determination is made as to whether the error count margin threshold of any of the at least some of the non-volatile memory blocks has been exceeded. A memory block management function is triggered upon determining that the error count margin threshold of any of the at least some of the non-volatile memory blocks has been exceeded.

Abstract: A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 16200 and a code rate of 10/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for 256-symbol mapping.

Abstract: A computing device includes an interface configured to interface and communicate with a dispersed storage network (DSN), a memory that stores operational instructions, and a processing module operably coupled to the interface and memory such that the processing module, when operable based on the operational instructions, is configured to perform various operations. The computing device determines data access rates corresponding respectively to storage units (SUs). In certain situations, the computing device selects at least a data access threshold number of SUs excluding a first slowest SU having the first slowest data access rate to service data access request(s) for set(s) of encoded data slices (EDSs) corresponding to a data object. The computing device facilitates servicing of the data access request(s) for the set(s) of EDSs by the at least a data access threshold number of SUs that excludes the first slowest SU having the first slowest data access rate.

Abstract: Based on a system configuration change (e.g., of a Decentralized, or Distributed, Agreement Protocol (DAP)) within a dispersed storage network (DSN), a computing device identifies a reallocating encoded data slice (EDS) number that is no more than a pillar width minus a performance threshold. The computing device then directs storage units (SUs) to update system configuration of the DAP (e.g., from a first to a second system configuration) by throttling and controlling the number of SUs permitted to update at a time. For example, the computing device permits no more than the reallocating EDS number of SUs to perform simultaneous (or substantially or approximately simultaneous) update of the system configuration of the DAP. The computing device also directs the SUs to operate based on the first system configuration before the condition(s) is/are met and then to operate based on the second system configuration after the condition (s) is/are met.

Abstract: A method and circuit for implementing enhanced scan data testing with decreased scan data interdependence for compressed patterns in on product multiple input signature register (OPMISR) testing through scan skewing, and a design structure on which the subject circuit resides are provided. The circuit is divided into multiple chiplets. Each chiplet includes a stump mux structure including multiple stump muxes connected in series, and a respective chiplet select is provided on shared scan inputs to respective chiplets. The chiplet select gates scan clocks, and when a chiplet is not selected the chiplet retains its data. The chiplet select enables test data to be skewed as scan data enters each chiplet.

Abstract: There are disclosed computer-implemented methods, apparatus, and computer program products for managing data storage. In one embodiment, the computer-implemented method comprises the step of receiving new data to be written to storage. The method also comprises the step determining that the new data does not form a full stripe of data. The method also comprises reading missing non-parity data in the stripe of data. The method further comprises determining new parity based on the new data and the missing non-parity data. The method still further comprises writing the new data and the new parity to storage in a manner that does not require the missing non-parity data to be written to storage.

Abstract: An integrated circuit operable in a scan mode includes a scan chain formed by cascaded flip-flop cells. Each flip-flop cell includes a master latch that receives a first data signal and generates a first latch signal, a slave latch that receives the first latch signal and generates a second latch signal, and a multiplexer having first and second inputs respectively connected to the master and slave latches that receives a first input signal and the second latch signal, and generates a scan data output signal depending on an input trigger signal. The first input signal is one of the first data signal and the first latch signal. The clock signal provided to the slave latch is gated by the input trigger signal.

Abstract: A nonvolatile memory system, a nonvolatile memory controller and a method for assuring retention are disclosed. The nonvolatile memory controller includes a retention monitor that stores test characteristics corresponding to a use case and determines, each time that a read of a codeword is performed, whether the number of errors in the codeword exceed a retention threshold. If the number of errors in the codeword exceed the retention threshold, the block containing the codeword is retired. The retention monitor performs retention tests during the operation of the memory controller and adjusts the retention threshold when the results of the retention tests indicate deviation from the test characteristics corresponding to a use case.

Abstract: A method of circuit yield analysis for evaluating rare failure events existing in multiple disjoint failure regions defined by a multi-dimensional parametric space, the method including performing initial sampling to detect failed samples respectively located at multiple failure regions in the multi-dimensional parametric space, performing clustering to identify the failure regions, performing feature filtering to determine which parameter component is a non-principal component in affecting circuit yield, applying a dimensional reduction method on a dimension corresponding to the parameter component, optimizing an importance sampling (IS) distribution function corresponding to each of the failure regions, and constructing a final importance sampling (IS) distribution function using a mixed Gaussian (mGaussian) function corresponding to all of the failure regions.

Abstract: A computing system includes: a data block including data pages and each of the data pages includes data sectors and each of the data sectors include sector data and a sector redundancy; a storage engine, coupled to the data block, configured to: apply a first protection across the data pages includes shifted parities generated, apply a second protection across the data sectors, and correct at least one of the data sectors when a sector correction with the sector redundancy failed by selecting one of the shifted parities for the first protection and the second protection.

Abstract: A logical storage layer for shared storage systems interposes between address ranges of the shards and the storage devices on which the shards are stored. The shards may be logically addressed using a plurality of addressable zones, to which the storage devices are independently mapped. Data requests related to a given piece of data associated with a shard may involve multiple storage devices, and vice versa.

Abstract: Bit-flip coding uses a bit-flip encoder to flip bits in a redundancy-intersecting vector of a binary array having n rows and n columns until Hamming weights of the binary array are within a predetermined range ? of n divided by two. Information bits of an input data word to the bit-flip coding apparatus are stored in locations within the binary array that are not occupied by n redundancy bits of a redundancy vector.

Abstract: Provided is a method for effectively suppressing packet losses by burst losses without an increase in delay by adaptively or fixedly changing a size of an FEC encoded block even when the number of packets per unit time is small. Each communication device 101 includes a transmitting unit 102 and a receiving unit 103. The transmitting unit 102 has a function of calculating forward error correction (FEC) codes based on the number of packets per encoding time and a value of a burst loss time of a network line. The receiving unit 103 decodes an FEC encoded packet and measures line quality information of the network for transmission to the transmitting unit 102. The transmitting unit 102 transmits the packets at equal intervals for as long as it is required for encoding, and can change a system for calculating FEC based on the burst loss time and the encoding time.

Abstract: Methods and apparatus deduplicate and erasure code a message in a data storage system. One example apparatus includes a first chunking circuit that generates a set of data chunks from a message, an outer precoding circuit that generates a set of precoded data chunks and a set of parity symbols from the set of data chunks, a second chunking circuit that generates a set of chunked parity symbols from the set of parity symbols, a deduplication circuit that generates a set of deduplicated data chunks by deduplicating the set of precoded chunks or the set of chunked parity symbols, an unequal error protection (UEP) circuit that generates an encoded message from the set of deduplicated data chunks, and a storage circuit that controls the data storage system to store the set of deduplicated data chunks, the set of parity symbols, or the encoded message.

Abstract: The present disclosure includes a redundant array of independent NAND for a three dimensional memory array. A number of embodiments include a three-dimensional array of memory cells, wherein the array includes a plurality of pages of memory cells, a number of the plurality of pages include a parity portion of a redundant array of independent NAND (RAIN) stripe, and the parity portion of the RAIN stripe in each respective page comprises only a portion of that respective page.

Abstract: Embodiments include methods, and computer system, and computer program products for testing directly and indirectly anchored interfaces for vulnerabilities regarding storage protection keys.