Abstract: A structure for radiofrequency applications includes a high-resistivity support substrate having a front face defining a main plane, a charge-trapping layer disposed on the front face of the support substrate, a first dielectric layer disposed on the charge-trapping layer, an active layer disposed on the first dielectric layer, at least one buried electrode disposed above or in the charge-trapping layer. The buried electrode comprises a conductive layer and a second dielectric layer.

Abstract: A system includes a radio frequency (RF) connector terminal that is configured to connect to an antenna, and a RF transmitter that transmits RF power to the RF connector terminal. The system further includes a power measurement unit that measures, as a first power measurement, first RF power of the RF transmitter power that is reflected via the RF connector terminal, and a controller that causes a transmission path discontinuity between the RF transmitter and the RF connector terminal. The power measurement unit further measures, as a second power measurement, second RF power of the RF transmitter power that is reflected from the discontinuity. The controller further determines if a first antenna is connected to the RF connector terminal based on the first and second power measurements.

Abstract: An information processing apparatus includes a central processing unit (CPU), a plurality of field-programmable gate arrays (FPGAs) connected to the CPU to communicate with the CPU, and a plurality of memories provided in a one-to-one relationship with the plurality of FPGAs. Each of the plurality of memories is configured to store configuration data of a corresponding one of the plurality of FPGAs. One of the plurality of FPGAs is configured to update the configuration data of each of the plurality of FPGAs stored in a corresponding one of the plurality of memories.

Abstract: A transformer assembly with shrinkage compensation during drying or curing of the windings including: a core having two yokes and two legs, a winding provided about at least one of the two legs of the core, the winding being insulated by an insulating material, a metal profile per yoke, extending in parallel to the respective yoke and being mounted to it, and two pistons seated in the metal profiles, the pistons being movable along their axial direction which is parallel to the longitudinal axis of the at least one winding, wherein the at least two pistons exert a force on the at least one winding in an axial direction of the windings.

Abstract: A high voltage switch comprising: a high voltage power supply providing power greater than about 5 kV; a control voltage power source; a plurality of switch modules arranged in series with respect to each other each of the plurality of switch modules configured to switch power from the high voltage power supply, and an output configured to output a pulsed output signal having a voltage greater than the rating of any switch of the plurality of switch modules, a pulse width less than 2 ?s, and at a pulse frequency greater than 10 kHz.

Abstract: A current matching circuit includes a plurality of LED driver circuits. A current to voltage converter circuit is coupled to the plurality of LED driver circuits to generate a plurality of voltage signals. Each one of the plurality of voltage signals is representative of a respective output current through a corresponding one of the plurality of LED driver circuits. A comparison circuit is coupled to the current to voltage converter circuit to compare the plurality of voltage signals. An adjustment circuit is coupled to the comparison circuit and the plurality of LED driver circuits. The adjustment circuit is configured to trim the plurality of LED driver circuits in response to the comparison circuit such that each respective output current through the plurality of LED driver circuits is substantially equal.

Abstract: A termination for a high-frequency transmission line includes a first resistor that has a first terminal coupled to a first end of a transmission line and a second terminal coupled to a first input/output pad, and a second resistor that has a first terminal coupled to the first input/output pad. The first resistor and the second resistor may provide a combined resistance that matches a nominal value of a characteristic impedance of the transmission line. The apparatus may include a third resistor having a first terminal coupled to a second end of a transmission line, and a second terminal coupled to a second input/output pad, and a fourth resistor having a first terminal coupled to the second input/output pad. The third resistor and the fourth resistor may provide a combined resistance that matches the nominal value of the characteristic impedance of the transmission line.

Abstract: Methods, systems, and apparatus for individual qubit excitation control with a global excitation drive. In one aspect, a method includes accessing a quantum system that comprises a plurality of qubits; a plurality of qubit frequency control lines, each qubit frequency control line corresponding to an individual qubit and controlling the frequency of the qubit; a driveline; a plurality of couplers, each coupler coupling a corresponding qubit to the driveline so that a plurality of qubits are coupled to the driveline; determining one or more qubits that require a rotation operation; for each qubit requiring a rotation operation: tuning the qubit frequency to the corresponding driveline frequency of the rotation operation; performing the rotation operation using a microwave pulse on the excitation drive; and tuning the qubit away from the driveline frequency of the rotation operation.

Abstract: A semiconductor system includes a semiconductor apparatus and an external apparatus. The semiconductor apparatus includes a calibration code generating circuit, a code shifting circuit, and a main driver. The calibration code generating circuit performs a calibration operation to generate a calibration code. The code shifting circuit changes, based on a shifting control signal, a value of the calibration code. A resistance value of the main driver may be set on the basis of the calibration code and a shifted calibration code. The external apparatus generates the shifting control signal based on the resistance value of the main driver.

Abstract: A quantum computing system is adapted to prepare a cat state in a quantum circuit with fault tolerance t and circuit depth less than or equal to 4+4t by performing a series of operations that includes: performing a sequence of joint parity measurements on individual pairs of neighboring qubits in a series of qubits entangled to form an initial cat state; repeating the sequence of measurements over at least t-rounds; and disentangling a first set of alternating qubits from the initial cat state, the prepared cat state being formed by a remaining second set of alternating qubits, the second set of alternating qubits being interlaced with the first set of alternating qubits along a line of one-dimensional connectivity, the series of operations being sufficient to guarantee that a prepared cat state is has less than or equal to t number of faults.

Abstract: A wideband termination circuit layout is provided for high power applications. The circuit layout may include a dielectric layer having a first surface and a second surface. The circuit layout may also include an input port disposed over the first surface. The circuit layout may further include at least two resistive film patches disposed over the first surface of the dielectric layer and a tuning line between the at least two resistive films disposed over the first surface of the dielectric layer. The at least two resistive film patches are connected in series with the at least one tuning line.

Abstract: A three-dimensional programmable interconnection system based on a multi-chip package includes: a programmable metal bump or pad at a bottom of the multi-chip package; a first programmable interconnect provided by an interposer of the multi-chip package; a second programmable interconnect provided by the interposer; and a switch provided by a first semiconductor chip of the multi-chip package, wherein the switch is configured to control connection between the first and second programmable interconnects, wherein the programmable metal bump or pad couples to a second semiconductor chip of the multi-chip package through the switch and the first and second programmable interconnects, wherein the first and second semiconductor chips are over the interposer.

Abstract: A load control device for controlling the amount of power delivered to an electrical load is able to operate in a normal mode and a burst mode. The load control device may comprise a control circuit that activates an inverter circuit during active state periods and deactivates the inverter circuit during inactive state periods. The control circuit may operate in the normal mode to regulate an average magnitude of a load current conducted through the electrical load to be above a minimum rated current. The control circuit may operate in the burst mode to adjust the average magnitude of the load current to be below the minimum rated current. The control circuit may adjust the average magnitude of the load current by adjusting the length of the inactive state periods while holding the length of the active state periods constant.

Abstract: Systems and methods for determining critical timing paths in a superconducting circuit design including Josephson junctions are provided. An example method includes providing timing information concerning a plurality of source terminals of at least one logic gate coupled with a first sink terminal of the at least one logic gate. The method further includes using a processor, determining whether, in view of the timing information, the first sink terminal is reachable by a single flux quantum (SFQ) pulse within a predetermined range of arrival time based on an assigned first phase to the at least one logic gate.

Abstract: An integrated circuit provides a semiconductor die with I/O bond pads, a power bond pad, and a circuit ground pad. Each I/O bond pad is associated with an input circuit that has an input circuit output lead. Sets of digital logic functional circuitry on the die provide different digital logic functions. Each function includes logic input leads and logic output leads. Output circuits each have an output circuit in lead and an output circuit out lead. Strapping structures, such as vias, formed in the semiconductor die electrically couple input circuits to a selected set of digital logic functions and the selected set of digital logic functions to output circuit in leads. Upper level metal conductors couple output circuit out leads and selected I/O bond pads.

Abstract: A method of handling integrated circuit dies with defects is provided. After forming a plurality of dies on one or more silicon wafers, test equipment may be used to identify defects on the dies and to create corresponding defect maps. The defect maps can be combined to form an aggregate defect map. Circuit design tools may create keep-out zones from the aggregate defect map and run learning experiments on each die, while respecting the keep-out zones, to compute design metrics. The circuit design tools may further create larger keep-out zones and run additional learning experiments on each die while respecting the larger keep-out zones to compute additional design metrics. The dies can be binned into different Stock Keeping Units (SKUs) based on one or more of the computed design metrics. Circuit design tools automatically respect the keep-out regions for these dies to program them correctly in the field.

Abstract: A chip package comprises an interposer; an FPGA IC chip over the interposer, wherein the FPGA IC chip comprises a programmable logic block configured to perform a logic operation on its inputs, wherein the programmable logic block comprises a look-up table configured to be provided with multiple resulting values of the logic operation on multiple combinations of the inputs of the programmable logic block respectively, wherein the programmable logic block is configured to select, in accordance with one of the combinations of its inputs, one from the resulting values into its output, and multiple non-volatile memory cells configured to save the resulting values respectively; multiple first metal bumps between the interposer and the FPGA IC chip; and an underfill between the interposer and the FPGA IC chip, wherein the underfill encloses the first metal bumps.

Abstract: A system includes a power source and a plurality of modules, where each module has a control for controlling a function of the module and a user input actuatable by a user. The plurality of modules are electrically connected in series with a power conductor electrically connected between each adjacent module, where the power source provides power to each module over the power conductor. In response to actuation by the user of the user input on a select module of the plurality of modules, the control of the select module generates a control signal that is transmitted to each other module over the power conductor, such that the control of each other module controls the associated function in the same manner as the select module.

Abstract: Provided are a quantum pulse determining method, apparatus, device and readable storage medium, where basic pulses corresponding to basic logic gates are set in advance, the method including: when manipulating a qubit according to a quantum logic gate, splitting the quantum logic gate to obtain sub-logic gates; and searching for sub-pulses corresponding to the sub-logic gates among the basic pulses, and manipulating the qubit according to the sub-pulse. Basic pulses are set in advance in the method, apparatus, device and readable storage medium provided by the embodiments. When a qubit is to be manipulated, the quantum logic gate can be split into multiple sub-logic gates, and then sub-pulses corresponding to the sub-logic gates are searched for among the basic pulses. Thus, sub-pulses read can be used directly to manipulate the qubit, avoiding the computing power consumed in generating pulses according to the quantum logic gate, thereby improving an operation speed.

Abstract: The disclosure describes various aspects of a practical implementation of multi-qubit gate architecture. A method is described that includes enabling ions in the ion trap having three energy levels, enabling a low-heating rate motional mode (e.g., zig-zag mode) at a ground state of motion with the ions in the ion trap; and performing a Cirac and Zoller (CZ) protocol using the low-heating rate motional mode as a motional state of the CZ protocol and one of the energy levels as an auxiliary state of the CZ protocol, where performing the CZ protocol includes implementing the multi-qubit gate. The method also includes performing one or more algorithms using the multi-qubit gate, including Grover's algorithm, Shor's factoring algorithm, quantum approximation optimization algorithm (QAOA), error correction algorithms, and quantum and Hamiltonian simulations. A corresponding system that supports the implementation of a multi-qubit gate architecture is also described.