Abstract: A single flux quantum (SFQ) circuit can include a combinational logic network, which can include a set of SFQ logic cells. The SFQ circuit can also include an SFQ sequencing circuit, which can be used to generate delayed versions of clock pulses to clock the set of SFQ logic cells.

Abstract: Memory devices and systems with per pin input/output termination and driver impedance calibration capabilities, and associated methods, are disclosed herein. In one embodiment, a device apparatus includes circuitry dedicated to an individual DQ pin of the device apparatus. The circuitry can be configured to (i) generate, at least in part, a voltage at the DQ pin based, at least in part, on an impedance internal to a host device electrically connected to the device apparatus and (ii) compare the voltage to a target voltage. Based, at least in part, on the comparison, the circuitry can be configured to adjust a resistance of an output driver and/or a termination circuit of the device apparatus that correspond to the DQ pin to adjust the impedance of the output driver and/or termination circuit to match an impedance associated with a corresponding input/output pin of the host device.

Abstract: A device includes an AND logic gate and a D latch. The AND logic gate includes a first input configured to be coupled to a third-party device to receive a selection signal, a second input configured to be coupled to the third-party device to receive a status signal, and an output configured to transmit an output signal when the selection signal and the status signal are received. The D latch is capable of storing datum. The D latch includes an activation input coupled to the output of the AND logic gate and a data input configured to be coupled to the third-party device to receive a data signal that is representative of the datum. The D latch is configured to store the datum in response to the output signal.

Abstract: The invention provides an apparatus comprising a programmable circuit including a plurality of 2-input 1-output ALUs, and an updating unit updating the programmable circuit according to circuit information, wherein each of the ALUs includes a calculation unit which performs a set type of calculation for two data and output a calculation result, a delay unit which delays the two input data in accordance with delay amounts independently set and supplies the delayed data to the calculation unit, and a controller which controls a delay amount for the delay unit and a calculation timing for the calculation unit in accordance with externally set information, wherein the updating unit sets clock gating start timings for a plurality of delay elements of the delay unit if an ALU of interest as a first processing circuit in the programmable circuit inputs final data to be processed.

Abstract: In a general aspect, a quantum computing method is described. In some aspects, a control system in a quantum computing system assigns subsets of qubit devices in a quantum processor to respective cores. The control system identifies boundary qubit devices residing between the cores in the quantum processor and generates control sequences for each respective core. A signal delivery system in communication with the control system and the quantum processor receives control signals to execute the control sequences, and the control signals are applied to the respective cores in the quantum processor.

Abstract: Apparatus and associated methods relate to an I/O bank impedance calibration circuit having (a) a replica master resistor coupled to an external precision resistor, and (b) a control circuit configured to calibrate an output impedance of the master resistor to generate a calibrated code to control a replica slave resistor in each bank. In an illustrative example, a signal applied to the replica master resistor may be compared against a programmable reference signal. The control circuit may generate the calibrated code, in response to the comparison result, to calibrate the output impedance of the replica master resistor. By implementing the replica master resistor and the replica slave resistor, impedances of a large number of IOs or banks may be calibrated by the impedance calibration circuit using a single one reference pin.

Abstract: In one embodiment, an RF impedance matching network utilizing at least one electronically variable capacitors (EVC) is disclosed. Each EVC includes discrete capacitors operably coupled in parallel, the discrete capacitors including fine capacitors and coarse capacitors. A control circuit determines a parameter related to the plasma chamber and, based on the parameter, determines which of the coarse capacitors and which of the fine capacitors to have switched in to cause an impedance match. The increase of the variable total capacitance of each EVC is achieved by switching in more of the coarse capacitors or more of the fine capacitors than are already switched in without switching out a coarse capacitor that is already switched in.

Abstract: The present disclosure relates to an electronic circuit having a three-dimensional design by comprising a set of two-dimensional electronic circuits, wherein the two-dimensional electronic circuits are coupled with each other by radiation. The disclosure further relates to a radar antenna system.

Abstract: In an integrated circuit including a clock gating cell based on a set-reset (SR) latch, the clock gating cell includes a first 2-input logic gate configured to receive a clock input and a first signal, and generate a second signal, a first inverter configured to receive the second signal, and generate a clock output, and a 4-input logic gate including a 4-input keeping logic gate configured to generate the SR latch by being cross-coupled to the first 2-input logic gate and keep a level of the first signal.

Abstract: In one embodiment, a switching circuit includes an electronic switch comprising one or more diodes for switching a reactance element within an electronically variable reactance element. A first power switch receives an input signal and a first voltage, and switchably connects the first voltage to a common output in response to the received input signal. A second power switch receives an input signal and a second voltage, and switchably connects the second voltage to the common output in response to the received input signal. The second voltage is opposite in polarity to the first voltage. The first power switch and the second power switch asynchronously connect the first voltage and the second voltage, respectively, to the common output, the one or more diodes of the electronic switch being switched according to the first voltage or the second voltage being connected to the common output.

Abstract: A power supply system for driving a light source includes a transformer including a primary winding and a plurality of secondary windings including an output bias winding, a control bias winding, and an RF bias winding, the output bias winding being electrically coupled to and configured to supply electrical power to the light source, a control circuit electrically coupled to and configured to receive electrical power from the control bias winding; and an RF communication circuit electrically coupled to and configured to receive electrical power from the RF bias winding.

Abstract: A semiconductor integrated circuit device includes digital output terminals and output circuits. Each output circuit includes a switch, and applies a potential, which corresponds to either one of binary logic levels, to corresponding one of the digital output terminals through the switch. An indefinite range is interposed between one of the binary logic levels and the other one of the binary logic levels. The output circuits respectively include potential fixers. Each potential fixer has an identical circuit arrangement, and the potential fixer fixes a potential applied to the digital output terminals through the switch to a potential corresponding to either one of the binary logic levels apart from the indefinite range, in response to that a short circuit occurs between the digital output terminals.

Abstract: A method, system, apparatus, and program for scheduling and controlling light towers in the field and receiving detailed reports relating to the same. The system for light tower control includes a telematics platform, a telematics device; and a light tower. The telematics platform is configured to transmit and receive a UDP message over a cellular network, wherein a transmitted UDP message contains a control signal for turning ON or OFF a light tower. The telematics device is configured to receive the UDP message and configure a voltage output of the telematics device based on the control signal. If the control signal is ON the voltage output of the telematics device is changed from Low to High and if the control signal is OFF the voltage output of the telematics device is changed from High to Low. A relay controller of the light tower turns the light tower ON if the output voltage of the telematics device is High and turns the light tower OFF if the output voltage of the telematics device is Low.

Abstract: An antenna system having a Vivaldi antenna configured to be impedance matched to antenna impedance Za at and above but not below a frequency fc; a Field-Effect-Transistor buffer coupled to the Vivaldi antenna, the length of the coupling between the antenna terminals and the buffer being of a distance much less than a wavelength at frequency fc, the buffer configured to present a high impedance at frequencies substantially <fc, the buffer output impedance further configured to be matched to a system impedance Z0 at frequencies both above and below fc.

Abstract: There is provided herein controllable power and lighting system. There is particularly provided a method for the arrangement and automatic control of one or more power consuming devices, including one or more light emitting diode (LED)-containing lighting devices, and optionally one or more non-LED based devices, wherein the devices are adapted to be powered by 3-phase AC power within the present systems.

Abstract: A method of configuring a programmable integrated circuit device. A channel source within the virtual fabric is configured to receive input data from a first kernel outside of the virtual fabric and on the programmable integrated circuit device, and a channel sink within the virtual fabric is configured to transmit output data to the first kernel. The configuring of the channel source is modified such that the channel source receives input data from a second kernel in response to detecting a change in operation of the programmable integrated circuit device.

Abstract: A chip antenna module includes a first dielectric layer; a solder layer disposed on a first surface of the first dielectric layer; a patch antenna pattern disposed on a second surface of the first dielectric layer; a coupling pattern disposed on the second surface of the first dielectric layer, and spaced apart from the patch antenna pattern without overlapping the patch antenna pattern in a thickness direction; a first feed via extending through the first dielectric layer in the thickness direction so as not to overlap the patch antenna pattern and the coupling pattern in the thickness direction; a first feed pattern extending from a first end of the first feed to overlap at least a portion of the coupling pattern; and a second feed pattern extending from a second end of the first feed via to overlap at least a portion of the coupling pattern.

Abstract: This disclosure describes techniques to control LED lighting systems using a circuit that includes communication, control and LED driver circuitry specific to a limited number of particular lighting functions. The circuit may communicate via a standard communication bus protocol and include feedback, protection and sensing circuitry to monitor the lighting functions and LED performance. The circuit may be small enough to be included as part of a lighting assembly, such as a vehicle headlight assembly. The included feedback and monitoring circuitry that may be physically close the driven LEDs may simplify the wiring when compared to other techniques. A configuration process for the circuit may further simplify the wiring connections, as well as reduce the development and manufacturing costs for lighting systems that may use the circuit. Limiting the lighting functions of each circuit may improve thermal management by distributing the thermal load.

Abstract: A system for monitoring the irradiation of an object with light from a luminaire includes the luminaire having one or more light sources, which emit light having a spatial radiation pattern; a computing unit, connected to the luminaire and set up to acquire information about an illuminance of the light of the light sources; a first memory, connected to the computing unit and in which information about spatial positioning of the luminaire relative to a surface of the object is stored; and a second memory, connected to the computing unit and in which information about the spatial radiation pattern of the light sources is stored. The computing unit may calculate and output a local intensity of light incident at the respective position on the basis of illuminance information, the spatial radiation pattern of the light sources, and the spatial positioning of the luminaire relative to the surface of the object.

Abstract: Quantum compression using quantum communication driver (QCD) computing devices employing superdense encoding of conventionally compressed files is disclosed. In one example, a first QCD computing device receives a compressed file that was compressed using conventional compression formats by a computing device. The first QCD computing device performs superdense encoding of the compressed file using one or more first qubits that are each in an entangled state with a corresponding one or more second qubits of a second QCD computing device. The first qubit(s) are then sent to the second QCD computing device. In some examples, the second QCD computing device generates a sequential qubit mapping that represents a sequence in which the one or more first qubits encode the compressed file, and stores the first qubit(s) in association with the sequential qubit mapping.