Abstract: A programmable logic array integrated circuit device includes a plurality of regions of programmable logic disposed on the device in a two-dimensional array of intersecting rows and columns of such regions. Each row has a plurality of adjacent horizontal conductors, and each column has a plurality of adjacent vertical conductors. The regions in a row are interspersed with groups of local conductors which interconnect the adjacent regions and the associated horizontal and vertical conductors. The local conductors can also be used for intra-region communication, as well as communication between adjacent regions. Secondary signals such as clocks and clears for the regions can be drawn either from dedicated secondary signal conductors or normal region inputs. Memory cell requirements for region input signal selection are reduced by various techniques for sharing these memory cells.

Abstract: An apparatus is described for regulating the flow of current through a load in which the flow of current is monitored in the form of a reference voltage by an analog input and a digital input of an arithmetic and logic unit. The voltage measured at the analog input is used to regulate the flow of current. The voltage measured at the digital input either as a low or as a high signal is used to switch off the flow of current when there is a low signal.

Abstract: A macrocell for a programmable logic device includes a carry generator for generating a carry input to the macrocell, the carry generator having an inverting input and at least one non-inverting input. A carry decoupler controls the carry generator and allows any macrocell to be decoupled from a next adjacent macrocell. An XOR gate having a first input is coupled to the output of the carry generator and a second input thereof is connected to a logic input to the macrocell. A register is coupled to the output of the XOR gate. A macrocell output selector includes a first input coupled to an output of the register and a second input coupled to the output of the XOR gate.

Abstract: A time borrowing domino circuit that includes complementary logic outputs and a multiplexor without incurring the time delays normally associated with complementary outputs and multiplexor function is described. A clock delay circuit is described which produces the trailing edge delay clock signal that drives the domino circuit. A domino circuit is described that may implement logical functions such as AND, OR, NAND, NOR, EXCLUSIVE-OR and EXCLUSIVE-NOR. A multiplexor circuit is described for gating one of a number of logical inputs to a latch. And a latch is described having complementary outputs.

Abstract: A technique for integrating an internal clock signal with various function commands in an integrated circuit device having an externally supplied clock signal to create a set of command clocks which have the same rising (or falling) edge time, duty cycle and duration and are, therefore, inherently clocked to ameliorate signal “race” and “skew” conditions encountered in prior designs. The technique of the present invention, therefore, improves overall device operational speeds in executing commands by reducing internal gate delays and resulting in faster data access times in integrated circuit memory devices such as synchronous dynamic random access memory (“SDRAM”) devices. Moreover, because the resultant design provides faster operation times, lower cost process technologies may be utilized to achieve substantially comparable performance levels.

Abstract: An output driver circuit for driving a signal onto a signal line. The output driver circuit comprises at least one driver circuit and a passive network. The passive network is configured to limit the variation in the output impedance of the output driver circuit. The output driver circuit thus provides an output impedance that closely matches the loaded impedance of the signal line at all times so as to minimize secondary reflections on the signal line.

Abstract: A personalizable and programmable integrated circuit device including at least first and second programmable logic cells and at least two electrical conductive paths interconnecting the programmable logic cells, at least a portion of which can be removed for personalization of the integrated circuit device.

Abstract: To provide a semiconductor integrated circuit having a CMOS circuit constituted by electrically connecting an n-type well 2, in which one transistor Tp for constituting the CMOS circuit is set, with a first power-supply-voltage line Vdd through a switching transistor Tps, and electrically connecting a p-type well 3 in which the other transistor Tn for constituting the CMOS circuit is set with a second power-supply-voltage line Vss through a switching transistor Tns. Moreover, the semiconductor integrated circuit is constituted so that thermal runaway due to leakage current can be controlled by turning off the switching transistors Tps and Tns and supplying a potential suitable for a test to the n-type well 2 and the p-type well 3 from an external unit when the semiconductor integrated circuit is being tested.

Abstract: A technique for reducing standby leakage current in a circuit block using input vector activation. A complex circuit includes a plurality of inputs and one or more transistor stacks. At least some of the transistor stacks are coupled to at least one of the inputs. The circuit also includes logic to apply a selected input vector to the plurality of inputs during a standby mode. The input vector is selected based on a configuration of the one or more transistor stacks in the circuit block to turn off a first number of transistors in the transistor stacks. The first number is within a selected percent of a maximum number of transistors in the transistor stacks that can be turned off by any vector applied at the plurality of inputs.

Abstract: A logic circuit which is driven at low voltage and operates at high speed and low power consumption is provided. Substrate potentials of P and N type transistors MP11 and MN11 constituting an inverter are controlled correspondingly to a stable state of the inverter. In a stable state of the inverter in which the P type transistor MP11 is ON, the substrate potential of the N type transistor MN11 which is OFF is lowered to ground potential or lower and, in a stable state of the inverter in which the N type transistor MN11 is ON, the substrate potential of the P type transistor MP11 which is OFF is raised to a power source potential or higher.

Abstract: A system and a method for calculating a value for the “Band Zero” (B∅) contribution to the processing of a digital signal by processing the separate parts of the signal at separate times. The method increases operating speed of a feedback circuit, for example, by providing a processing path (402f) that is not on the main high-speed processing path of a system such as a read channel of a disk drive. By processing the most time-consuming determination “in parallel,” the high-speed portion of processing is able to maintain an optimum throughput. The method also lends itself to processing in those applications where more than one mode is used. For example, when used in a read channel (113) of a disk drive (100) employing a FIR filter, three modes are desired: FIR-bypass, acquisition, and data tracking.

Abstract: A programmable bus hold circuit which may find application in programmable logic devices, memories and other I/O devices may include a first element for receiving a voltage from an I/O pad and programmable circuitry coupled to the first element for controlling whether the voltage at the pad is to be held its current logic level. The first element may be a logic gate (such as a NOR gate) the programmable circuit may include a tristatable buffer (e.g., under the control of a memory cell or other programmable bit capable of enabling or disabling the programmable bus hold circuit) or a switch (e.g., a transistor).

Abstract: A Field Programmable Gate Array (FPGA) device includes a plurality of input/output blocks (IOBs) and variable grain blocks (VGBs). An inter-connect network provides efficient and flexible routing of control signals from VGBs to IOBs. Control signals may include individual control signals to a predetermined IOB or common control signals to a plurality of IOBs. The inter-connect network includes vertical and horizontal inter-connect channels. The inter-connect channels are coupled to switch boxes having line segments or stubs. The line segments are coupled to an IOB control multiplexer which output control signals to IOBs. The use of stubs allows for efficient and flexible use of interconnect resources.

Abstract: A programmable logic device includes a global clock structure and a plurality of localized clock structures. Each localized clock structure distributes a respective localized clock signal to a corresponding portion of the programmable logic device. The global clock structure distributes a global clock signal to all portion of the programmable logic device.

Abstract: High-speed signal translators are provided to convert differential input signals (e.g., ECL signals) to single-ended output signals (e.g., CMOS signals). An exemplary translator is formed with first and second current mirrors, first and second complimentary differential pairs of transistors, a complimentary transistor output stage and first and second current-diverting transistors. The complimentary output stage initially generates the single-ended output signal in response to currents received from the complimentary differential pairs. When the output signal has been established, the current-diverting transistors respond by carrying at least portions of the currents supplied by the complimentary differential pairs. The current-diverting transistors also drive the current mirrors to divert other portions of these currents away from the complimentary output stage. Stored charges in the output stage are accordingly reduced and its response time enhanced.

Abstract: A method for terminating signals in an information handling system comprises includes providing a plurality of resistance elements, providing at least three transmission lines each having a characteristic impedance, each of the transmission lines having a first end, each of the first ends being coupled together through said resistance elements, and a second end, and providing a plurality of drivers equaling the number of transmission lines in the plurality of transmission lines, each driver coupled to a second end of a different one of the transmission lines, each driver comprising a pull-down circuit having a pull-down resistance matched to the characteristic impedance of one of the lines, and a pull-up circuit having a pull-up resistance corresponding to the number of second ends.

Abstract: A logic circuit arrangement includes signal input and signal output devices and a number of SFQ circuits having Josephson junctions in which carrier devices are used for carrying digital information. The SFQ circuits are sampled at the input/output for producing DC voltages and a train having at least two single flux quanta is used as a carrier device for information and phase locking between at least two Josephson junctions is used to provide at least two different dynamic states of which at least one provides an output signal.

Abstract: An output buffer comprising control circuit for reducing the amount of ground and/or power bounce noise. The output buffer further includes one or more driver devices. The output current of the driver device(s) is limited by providing an intermediate drive voltage to the control electrode of the driver device. A pass device (or a transmission gate) provides the intermediate drive voltage and also operates as a variable resistive device that limits the slew rate of the drive voltage. The operation of the pass device can be dependent on a signal level at the output of the output buffer. When the output has transitioned to a new logic state, the new logic level is fed back to change the operating state of the pass device, thus ensuring that the output voltage meets the output VOL and VOH specifications.

Abstract: A method and apparatus for detecting whether dynamic logic circuits are precharging properly. The method and apparatus uses a narrowed reset pulse to verify precharging is occurring as designed.

Abstract: A field-programmable gate array device (FPGA) having plural rows and columns of logic function units (VGB's) further includes a plurality of embedded memory blocks, where each memory block is embedded in a corresponding row of logic function units. Each embedded memory block has an address port for capturing received address signals and a controls port for capturing supplied control signals. Interconnect resources are provided including a Memory Controls-conveying Interconnect Channel (MCIC) for conveying shared address and control signals to plural ones of the memory blocks on a broadcast or narrowcast basis.