Abstract: An FPGA architecture has top, middle and low levels. The top level of the architecture is an array of the B16×16 tiles arranged in a rectangular array and enclosed by I/O blocks on the periphery. On each of the four sides of a B16×16 tile, and also associated with each of the I/O blocks is a freeway routing channel. A B16×16 tile in the middle level of hierarchy is a sixteen by sixteen array of B1 blocks. The routing resources in the middle level of hierarchy are expressway routing channels M1, M2, and M3 including groups of interconnect conductors. At the lowest level of the semi-hierarchical FPGA architecture, there are block connect (BC) routing channels, local mesh (LM) routing channels, and direct connect (DC) interconnect conductors to connect the logic elements to further routing resources.

Abstract: A method and apparatus for implementing dynamic logic with programmable dynamic logic gates acts as a complement to programmable logic arrays (PLAs) used in high-speed microprocessor designs. A matrix of selectable cells provides powerful logic functions such as AND-OR gate capability with a minimum of inputs and transistors. By using programmable logic arrays and programmable dynamic gates, the efficiency of a logic block can be dramatically improved with little added circuit area.

Abstract: A programmable output driver is comprised of a first signal path for pulling an output node up to a first voltage level and a second signal path for pulling the output node down to a second voltage level. A plurality of capacitors and a plurality of switches are provided for programmably connecting certain of the plurality of capacitors to the second signal path to control the falling edge of a signal output from the driver. In a preferred embodiment, the first signal path includes a boot circuit which primarily controls the leading edge of the signal output from the driver. A method of operating an output driver is also disclosed.

Abstract: A chip's interface is selected by using a fuse option coupled between integrated circuitry on the chip and logic circuitry. Fuse options correspond to antifuses or fuses. In one embodiment, a plurality of fuse options are manufactured in an integrated circuit such that a fuse option is coupled between integrated circuitry on the chip and separate and complete logic circuitry for different logic types used to interface a chip. In another embodiment, only one type of logic circuitry is manufactured on a chip, such that the logic circuitry has both a pull-up and pull-down transistor. A fuse is coupled with a pull-up control circuit of the logic circuitry. When the fuse is blown, the output circuit corresponds to GTL-terminated logic circuitry, using only the pull-down transistor. In a further embodiment, an antifuse is coupled with the pull-up control circuit.

Abstract: A current-mode bidirectional input/output buffer circuit for impedance matching and operation at a high speed. The current-mode bidirectional input/output buffer circuit communicates with an external chip having the same current-mode bidirectional input/output buffer. In the buffer, a transmitting-receiving average voltage output unit converts an average current value between a transmission signal to be transmitted to the external chip and a receiving signal transmitted from the external chip, into an average voltage. A reference voltage output unit converts a reference current value selectively generated according to a voltage level of the transmission signal, into a reference voltage. A comparator compares the voltage from the transmitting-receiving average voltage output unit to the voltage from the reference voltage output unit to provide a logic signal corresponding to the received signal transmitted from the external chip.

Abstract: A logic element for a programmable logic device to implement a lonely register architecture. The logic element includes logic modules (P0-P4) for implementing combinatorial logic and a register (445). The combinatorial and registered paths of a logic element may be utilized at the same time. The logic modules may be programmably coupled to the register. The output of the register may be programmably coupled through an output buffer (515) to an I/O pad (520) of the integrated circuit. The logic modules may bypass the register and directly programmably couple through the output buffer to the I/O pad. A logic module may be used as a shareable expander by programmably coupling the module through to a global interconnect with other logic modules in LABs coupled to the global interconnect.

Abstract: A logic element (300) for a programmable logic device. The logic element (300) allows two independent logic functions to be carried out during the same clock cycle. A 4-input look-up table (406) is provided using a 3-input look-up table (434) and two 2-input look-up tables. The results of the 4-input lookup table (406) and the 3-input lookup table (434) may be routed simultaneously from the logic element. It also allows a signal to be routed through a logic element (300) while carrying out an independent logic function. Carry logic (425) is provided. The results of the carry logic (486) may be routed to the global and local interconnect structure of the programmable logic device.

Abstract: Circuitry is provided to individually configure each I/O of an integrated circuit to be compatible with a different LVTTL I/O standards. This can be done with only one I/O supply voltage, where that voltage is the highest of the I/O voltages needed in a particular application. The circuitry operates by regulating the output voltage of the I/O cell so that it is above the VOH and below the maximum VIH for the LVTTL standard for which it will comply with. Since each I/O cell is individually configurable, any I/O can drive out to any LVTTL specification.

Abstract: The present invention relates to a mechanical coder. The mechanical coder includes a gear-shaped and conductive signal-separating wheel having a plurality of recesses. Each of the recesses of the signal-separating wheel is filled with insulating material to form a plurality of insulating portions. The surface of the signal-separating wheel is smooth so that the topography is avoided. The mechanical coder further includes a terminal module consisting of a first terminal, a second terminal and a common terminal. The common terminal is coupled to the conductive portion so that the common terminal is normally “ON”. The first terminal and the second terminal are coupled to the opposite side of the signal-separating wheel, respectively.

Abstract: A buffer circuit utilizes a single gate oxide pre-buffer voltage level shifting circuit on, for example, an output buffer of an I/O pad, to accommodate different I/O pad supply voltages while maintaining normal operating voltages (degradation levels) across boundaries of single gate oxide devices that form the buffer. The single gate oxide output buffer can operate at several different supply voltages. A pre-buffer voltage level shifting circuit includes a multi-supply voltage level shifting circuit having signal gate oxide devices coupled to produce a pre-buffer output signal to an output buffer. A single gate oxide cross coupled active load is coupled to the multi-supply voltage level shifting circuit and provides suitable drive voltages to at least one of cascaded buffer transistors.

Abstract: An FPGA architecture has top, middle and low levels. The top level of the architecture is an array of the B16×16 tiles arranged in a rectangular array and enclosed by I/O blocks on the periphery. On each of the four sides of a B16×16 tile, and also associated with each of the I/O blocks is a freeway routing channel. A B16×16 tile in the middle level of hierarchy is a sixteen by sixteen array of B1 blocks. The routing resources in the middle level of hierarchy are expressway routing channels M1, M2, and M3 including groups of interconnect conductors. At the lowest level of the semi-hierarchical FPGA architecture, there are block connect (BC) routing channels, local mesh (LM) routing channels, and direct connect (DC) interconnect conductors to connect the logic elements to further routing resources. Each B1 block includes four clusters of devices. Each of the four clusters includes first and second LUT3s, a LUT2, and a DFF .

Abstract: A matched filter arrangement and an FPGA-implemented tap arrangement for a matched filter are described in various embodiments. In an n-tap filter to match a code sequence, each of taps 1 through (n-1) includes a configurable adder-subtractor. A code storage element is coupled to the adder-subtractor to select either addition or subtraction in accordance with a corresponding bit of the code sequence. The output of the adder-subtractor is coupled to a partial-result storage element, which is part of a chain of partial-result storage elements. The last partial-result storage element in the chain is coupled to the data input of an adder-subtractor in another tap. The last tap includes an adder-subtractor and a single storage element for storage of the final result.

Abstract: A logic isolation circuit has a transmitter circuit for receiving a logic input signal and providing a periodic signal to an isolation barrier, and a receiving circuit for receiving the periodic signal from the isolation barrier and for providing an output signal that indicates the transitions in the logical input signal.

Abstract: A clock signal generator enables a clock signal having the same duty ratio as unchanged original duty ratio of original signal whose edge already had become dull to be generated in spite of simple constitution. A first and a second clock signals are outputted through open collector corresponding to respective “H” level and “L” level of an original clock signal. Only a trailing edge together with sharp change of speed of the clock signal is used. An output clock signal whose duty ratio is the same as that of the original clock signal is generated by obtaining exclusive OR of both of these clock signals, while implementing ½-times frequency division to the first and the second clock signals.

Abstract: A buffer circuit for mixed voltage applications. The circuit is built from field effect transistors and is used to interface with multiple voltage levels. The circuit uses a protection transistor in which the gate is controlled by a logic circuit having the mixed voltages as inputs. It is particularly useful on CMOS semiconductor chips that interface with multiple voltage levels which are required to conform to a specification allowing voltage levels to be powered down.

Abstract: A signal level shifting circuit comprises an emitter-follower transistor with a base supplied with an input signal, a collector coupled to a supply voltage, and an emitter coupled via a level shifter to a bias circuit, whereby a level shifted signal is produced at a junction point between the level shifter and the bias circuit. The level shifter comprises one or more diodes to provide a forward voltage drop providing a signal level shift, a PMOS transistor switch in parallel with the diode(s), and a control circuit responsive to the supply voltage for controlling the switch to bypass the diode(s), thereby providing a smaller level shift, when the supply voltage has a lower one of two possible values. The circuit can have a differential input and a differential output stage, and cascode-connected transistors for reducing voltages so that the circuit can be implemented using BCMOS technology.

Abstract: A spare gate cell on a integrated circuit contains both a configurable logic gate and one or more inverters. Inputs of these circuits have an appearance, accessible by the automatic place-and-route tool, at the topmost metal layer on the integrated circuit, which is metal 3 or higher. The outputs of the circuit preferably are accessible up to the same metal layer. The combination of the configurable gate circuit and one or more inverters enables any one such cell to selectively implement a wide range of logic functions by making appropriate connections during fib-mill processing of the integrated circuit device. The use of interconnections at the topmost layer facilitates reconfiguring a circuit to implement desired logic and interconnection thereof into the pre-defined logic on the integrated circuit. The inventive spare gate cells provide a high degree of design flexibility, both for circuit debug operations and for implementation of enhanced logic functions.

Abstract: This invention provides a structure and method for improved transmission line operation on integrated circuits. A first embodiment of this invention provides a current mode signaling technique over transmission lines formed having a lower characteristic impedance than conventional CMOS transmission lines. The low impedance transmission lines of the present invention are more amenable to signal current interconnections over longer interconnection lines. An interconnection on an integrated circuit is described in which a first end of a transmission line is coupled to a driver. The transmission line is terminated at a second end with a low input impedance CMOS technology. In one embodiment, the low input impedance CMOS technology is a current sense amplifier which is input impedance matched to the transmission line. This minimizes reflections and ringing, cross talk and noise as well as allows for a very fast interconnection signal response.

Abstract: A Dynamically Terminated Bus (DTB) comprising a transmission line coupled to a plurality of dynamically configurable components and a bus protocol that only permits a single component to transmit at a time. Each of the dynamically configurable components can be configured as a single unbalanced complementary metal-oxide-semiconductor (CMOS) pull-up driver and a gunning transceiver logic (GTL) on-die, pull-up termination receiver. However, only one dynamically configurable component can be configured as the CMOS pull-up driver at a time. Embodiments of the present invention provide a high speed, DTB for coupling to the components.

Abstract: An apparatus for high speed signal propagation across a net in an integrated circuit operates with a driver that is coupled to the net, for driving signals across the net. A first transition assist driver (TAD) is coupled to a first node in the net and is capable of pulling the voltage level of the first node in response to the voltage level of the first node reaching a threshold value. The threshold value can be adjusted in order to increase the switching speed or, alternatively, the noise immunity of the first TAD. A second TAD is coupled to a second node in the net and is capable of pulling the voltage level of the second node in response to the voltage level of the second node reaching the threshold value. The apparatus is used for increasing the propagation speed of signals that are transmitted in a microprocessor block or other stages in an integrated circuit.