Abstract: An information handling system is disclosed herein. The system includes at least one system transmission line having a characteristic impedance and a plurality of clusters, each cluster being coupled to each other cluster through at least one of the system transmission lines. Each cluster comprises at least one cluster transmission line each having a characteristic impedance equal to the characteristic impedance of the system transmission lines, and is coupled to a the system transmission line and a circuit chosen from the following: a driver, an on-chip terminator, an off-chip terminator; each driver having a pull-up circuit having an output resistance matching the characteristic impedance of the cluster transmission lines.

Abstract: An attenuating circuit for reducing the inductively induced voltage transients in an electrical signal. The attenuating circuit is formed by a primary circuit and a smoothing circuit both coupled to a voltage source through an inductive conductor. The primary circuit operates in two states having a first and second current draw, respectively. The smoothing circuit also has a first and second state and a first and second current draw, respectively. The current draws of the primary circuit and the smoothing circuit are such that the total current draw on the voltage source through the inductive conductor maintains relatively constant regardless of the state that the primary circuit is in, thus minimizing any induced voltage transients as a result of the conductor's inductance.

Abstract: A first MOS transistor and a second MOS transistor are interconnected in series. Basically, a set of these MOS transistors are alternately turned on according to a switching signal. The collector of a third transistor is connected to the gate of the second MOS transistor. A capacitor is provided between the base of the third transistor and the connection point between the first MOS transistor and the second MOS transistor.

Abstract: An output buffer includes a continuously variable output impedance proportional to the load transmission line impedance. The buffer includes an output stage, such as a pullup/pulldown transistor, for receiving an input signal and generating an output signal on an output node in response thereto. In addition, the buffer includes a control circuit and a low-impedance driver in an electrical communication with the output node and, preferably, disposed in parallel with at least one of the pullup and/or pulldown transistors. The control circuit receives the output node voltage and generates a control signal on a control node that varies according to the magnitude of the output node voltage. The driver is biased by the control signal and has a conductivity that varies according to the control signal. The variations in the conductivity are operative to adjust the output impedance of the buffer.

Abstract: The differential mode gate includes a first load resistance having a first current driving capability. The first load resistance is connected to a power supply voltage. A constant current source, having a second current driving capacity, is connected to ground. A first logic gate is connected between the first load resistance and the constant current source. The first logic gate performs a first logic operation on received inputs to generate a first output. The differential mode gate additionally includes a second load resistance and a second logic gate. The second load resistance has a third current driving capability and is connected to the power supply voltage. The second logic gate is connected between the second load resistance an the constant current source, and performs a second logic operation on the received inputs to generate a second output.

Abstract: A programmable logic integrated circuit device has a plurality of areas of programmable logic disposed on the device in a two-dimensional array of intersecting rows and columns of such areas. A so-called “fast conductor” network is provided on the device for rapidly and efficiently distributing a relatively small number of signals to substantially any logic area on the device. The fast conductor network has several main conductors that substantially bisect the array in one direction (e.g., by extending parallel to the column axis). Some main conductors can carry signals from off the device. Other main conductors can carry signals generated on the device. The network further includes secondary conductors that extend transverse to the main conductors (e.g., along each row of logic areas). Programmable logic connectors are provided for selectively applying signals from the main conductors to the secondary conductors and from the secondary conductors to the logic areas.

Abstract: A programmable logic device has a plurality of conductors extending around its periphery for use in providing at least some of the signals needed for control of input/output (“I/O”) pins which are also disposed around the periphery of the device. These control signals may include clock signals, output enable signals, clock enable signals, clear signals, or the like. The conductors that thus extend around the periphery are segmented into plural segments that can either be used independently of one another or programmably stitched together and therefore used together.

Abstract: A control scheme for operating an oscillator/counter A/D converter so that it simultaneously provides frequency downconversion, band pass filtering and analog-to-digital conversion of an analog signal, where the analog signal includes a carrier wave modulated with information by any known modulation technique. The converter uses a superconducting, Josephson single flux quantum circuit operating as a voltage controlled oscillator. The voltage controlled oscillator receives the analog signal to be converted, and generates a series of sharp, high frequency pulses based on the characteristics of the carrier signal. The series of pulses are applied to a gate circuit that, depending on a gate control signal, either blocks the pulses or passes the pulses to either an increment or a decrement port of a digital counter. When the pulses are passed by the gate circuit, the counter circuit accumulates the pulses during a sampling period.

Abstract: A method for routing a conductive path in an integrated circuit is described. The method includes providing a side exiting bus comprising at least one pin, and providing a plurality of functional units, at least one functional unit having a pin required to be electrically connected to a pin in the side-exiting bus. The method further includes routing a first conductive path from one of the at least one pins in the side exiting bus to a point external to the functional units, the resulting conductive path spanning the width of the plurality of functional units, and routing a second conductive path in a straight line from the at least one pin in the at least one functional unit to a point on the first conductive path.

Abstract: A programmable logic device integrated circuit incorporating a first-in, first-out memory block (250). First-in, first-out memory block (250) is coupled to a programmable interconnect array (213). Signals from the logic array blocks (LABs) (201) are connected to the control inputs of the first-in, first-out memory (250). In one embodiment, the programmable interconnect array (213) may be programmably coupled to the control inputs (259) of the first-in, first-out memory block. Status flag signals (276) from the first-in, first-out memory block (250) are programmably coupled to the programmable interconnect array (213). Data input (263) and data output (261) to first-in, first-out memory block (250) may be coupled to external, off-chip circuitry.

Abstract: The invention provides a structure and method of generating a clock enable signal in a programmable logic device (PLD). A first embodiment of the invention comprises a clock enable circuit implemented such that the critical paths have only two levels of logic. In this embodiment, the critical paths are implemented in dedicated logic while other portions of the clock enable circuit are implemented using programmable logic. According to another embodiment of the invention, the clock enable circuit is located near the center of a first edge of the device. A first plurality of output registers are located along the first edge on either side of the clock enable circuit, with additional output registers being located along the two adjacent half-edges. Programmable interconnection points (PIPs) permit a clock enable interconnect line along the first edge to be programmably extended to the additional output registers. In another embodiment, the clock enable circuit is duplicated in two opposite edges of the device.

Abstract: A ripple-data function unit having a ripple function and a data function for use in a priority circuit is described. The ripple-data function unit may be used to implement a priority encoder or a priority to 1-HOT recoder simply by defining the ripple and data functions as Boolean functions representing the ripple and arithmetic characteristics of the priority circuit desired. For example, at least one instance of a ripple-data function unit may be used to define a priority encoder if each instance includes ripple and data functions equivalent to the ripple and arithmetic characteristics of the priority encoder. Similarly, at least one instance of ripple-data function unit may be used to define a priority to-1-HOT recoder if each instance includes ripple and data functions equivalent to the ripple and arithmetic characteristics of the priority to 1-HOT recoder.

Abstract: A data transfer device having a post charge logic circuit which utilizes signals on a pair of data lines performs a post charge operation on the other a plurality of data line pairs. A data transfer device uses only signals on a pair of data lines to perform the post charge operation to the other data lines, thereby reducing the area of the memory device.

Abstract: An asynchronous sensing differential logic circuit using a charge-recycling technique includes a control block carrying out a logical operation on a request signal from a preceding stage and a request signal for a succeeding stage, and outputting a first or second input enable signal and a first or second clock signal, a functional block carrying out an operation on an input data according to the first or second input enable signals and the first or second clock signals from the control block, and outputting a first or second output enable signal and an output data, and a latch block triggered by an acknowledge signal from the succeeding stage, and outputting a request signal for the succeeding stage and a final output data by carrying out an operation on the first or second output enable signals and the output data from the functional block.

Abstract: A signal transmission system includes a first circuit block having a first output circuit for producing a first signal, a plurality of second circuit blocks each including a first receiving circuit for receiving the first signal, and transmission lines connected between the first circuit block and the second circuit blocks, wherein the first circuit block further includes a second output circuit for producing a second signal, and wherein each of the second circuit blocks further includes a second receiving circuit for receiving the second signal, the first receiving circuit latching the first signal in synchronism with the second signal, removing the unsuccessfulness in the signal transmission and reception due to the propagation delay of signals between circuits.

Abstract: A digital concatenator, the operation of which is triggered by the sequential arrival of a series of n-bit bytes thereto, accepts such sequential n-bit bytes and, by directing those n-bit bytes into sequentially identified n-bit channels, concatenates those n-bit bytes into (n×m)-sized words, where m is a pre-selected integral number of said n-bit bytes that are desired to be concatenated within an (n×m)-sized output buffer into a resultant sequence of (n×m)-sized words. The sequential identification of those n-bit bytes is brought about by a cyclical counter incorporated within a data enumerator that counts off the arrival of each n-bit byte and appends a corresponding position bit or byte to each one thereof. Each successive reading of the output of the concatenator is triggered by the arrival at that output buffer through an mth channel of an mth n-bit byte. The concatenator similarly operates on single bits so as to serve as a serial to parallel converter of arbitrarily selectable size.

Abstract: A programmable logic array is provided. The programmable logic array includes first and second logic planes. The first logic plane receives a number of input signals. The first logic plane includes a plurality of vertical transistors arranged in rows and columns that are interconnected to provide a number of logical outputs. The second logic plane also includes a number of vertical transistors arranged in rows and columns that receive the outputs of the first logic plane and that are interconnected to produce a number of logical outputs such that the programmable logic array implements a logical function.

Abstract: The present invention achieves the stated input receiver goals by merging many of the different functions required into a single unit instead of serializing them in the more traditional fashion. The present invention provides a receiver circuit having both a source-follower pair of MOS transistors, and a source-coupled pair of MOS transistors. The connecting node between these two pairs is coupled to a sense amplifier. The simultaneous use of the source-follower pair, the source-coupled pair and the sense-amplifier transistors allows for fast amplification of the low-swing input to full-rail CMOS, when triggered by a CMOS input clock.

Abstract: A logic block in a product-term based programmable device comprising a first logic gate, a second logic gate, a macrocell and a multiplexer. The first logic gate may be configured to generate a first output in response to a logical combination of a first number of product terms. The second logic gate may be configured to generate a second output in response to a logical combination of a second number of product terms. The macrocell may be configured to generate a third output in response to the second output. The multiplexer may be configured to select an output of the device in response to (i) the first output or (ii) the third output. The first number of product terms may be a subset of the second number of product terms.

Abstract: A method of controlling a slew rate includes applying a resistive load to a bus corresponding to the number of logic components in a computer. The number of logic components within the computer is varied by either adding or removing a logic component. A second resistive load is selected to be applied to the bus after the number of logic circuits in the computer has been changed. The selection of a second resistance enables the slew rate to be controlled when the number of components change.