Patents Examined by Don Phu Le
  • Patent number: 6498512
    Abstract: An apparatus includes a clock generator configured to generate a series of new clock pulses, the clock generator having an input port for receiving input clock pulses, an output port for delivering the new clock pulses to a target circuit that uses the new clock pulses to determine at least a start time or a stop time of a signal generated by the target circuit, and, a pulse delay for governing the width of the new clock pulses, the delay including circuits that produces longer delays for faster corners.
    Type: Grant
    Filed: February 27, 2001
    Date of Patent: December 24, 2002
    Assignee: Intel Corporation
    Inventors: Thomas D. Simon, Rajeevan Amirtharajah
  • Patent number: 6498543
    Abstract: A monoblock dielectric duplexer comprises resonant holes. Conductive electrodes and couplers are formed on one side of the dielectric block, whose other sides are covered with a conductive material. The conductive electrodes in a transmit-filtering portion are formed in an inter-digitating manner while the conductive electrodes in receive-filtering portion are formed to be of pad-shape. In the duplexer, capacitances of capacitors comprised of the conductive electrodes are easily and accurately set to desired values by determining the number and/or the lengths of fingers that the inter-digitating electrodes have.
    Type: Grant
    Filed: June 19, 2001
    Date of Patent: December 24, 2002
    Assignee: Korea Institute of Science and Technology
    Inventors: Hyun Jai Kim, Seok Jin Yoon, Ji Won Choi, Chong Yun Kang, Hyeung Kwon Choi
  • Patent number: 6496032
    Abstract: In accordance with an embodiment of the present invention, an integrated circuit includes an input bus configured to receive a plurality of input signals. The input bus extends across a predetermined length of one side of the integrated circuit. The integrated circuit further includes a plurality of logic block circuits coupled to the input bus for receiving one or more of the input signals. Each of the logic block circuits are coupled to at least one of a plurality of destination blocks via a first set of interconnect buses. The logic block circuits are placed along the one side of the die such that the first set of interconnect buses extend substantially orthogonal to the input bus.
    Type: Grant
    Filed: June 29, 2000
    Date of Patent: December 17, 2002
    Assignee: C-Link Technology
    Inventor: Jong-Hoon Oh
  • Patent number: 6496031
    Abstract: A method for calculating the P/N ratios of static gates based on the voltages presented at the inputs of these static gates. The method identifies the PFETs and NFETs that are used when a particular voltage pattern drives the input of a static gate. After the FETS have been identified, a maximum and minimum P/N ratio is calculated. A maximum and minimum P/N ratio is determined in order provide more accurate models for simulating problems, for example, noise on the inputs. Using the PIN ratios created by this method, integrated circuit designers can create computer simulations that better model the electrical environment that integrated circuits operate in and most likely reduce the probability that the particular integrated circuit they are designing will have design errors.
    Type: Grant
    Filed: April 30, 2001
    Date of Patent: December 17, 2002
    Assignee: Hewlett-Packard Company
    Inventors: S Brandon Keller, Gregory D Rogers
  • Patent number: 6496034
    Abstract: Structures and methods for programmable logic arrays are provided. In one embodiment, the programmable logic array includes a first logic plane and a second logic plane. The first logic plane receives a number of input signals. The first logic plane has a plurality of logic cells arranged in rows and columns that are interconnected to provide a number of logical outputs. The second logic plane has a number of logic cells arranged in rows and columns that receive the outputs of the first logic plane and that are interconnected to produce a number of logical outputs such that the programmable logic array implements a logical function. Each of the logic cells includes a vertical pillar extending outwardly from a semiconductor substrate. Each pillar includes a single crystalline first contact layer and a second contact layer separated by an oxide layer. Each logic cell further includes at least one single crystalline ultra thin vertical transistor that is selectively disposed adjacent the vertical pillar.
    Type: Grant
    Filed: February 9, 2001
    Date of Patent: December 17, 2002
    Assignee: Micron Technology, Inc.
    Inventors: Leonard Forbes, Kie Y. Ahn
  • Patent number: 6492836
    Abstract: A receiver circuit provides a first stage having an input for receiving input signals and an output node. The first stage includes an amplifier. A second stage has an input coupled to the output of the first stage. The second stage includes a switching circuit coupled to the output node of the first stage for driving the input signals by favoring a rising edge or a falling edge in accordance with a control signal. The second stage also includes a feedback loop coupled to an output of the second stage. The feedback loop provides the control signal for switching the switching circuit to favor the rising edge or falling edge.
    Type: Grant
    Filed: November 30, 2000
    Date of Patent: December 10, 2002
    Assignee: Infineon Technologies AG
    Inventor: Oliver Kiehl
  • Patent number: 6492838
    Abstract: In one embodiment, a circuit is provided that includes a precharge device, a DNG FET transistor, and at least one pull-down FET transistor with a floating body. The precharge device is connected to a precharge node for charging it during a precharge state. The DNG FET transistor is connected between a DNG node and a charge sink for operably linking the DNG node to the charge sink during an evaluate state. In addition, the DNG transistor has an associated precharge leakage current. The at least one pull-down FET transistor has an input threshold voltage whose value is inversely affected by its floating body voltage. The at least one pull-down transistor is connected between the precharge node and the DNG node for discharging the precharge node during the evaluate state if so dictated by logical function input values applied to the pull-down transistors during the evaluate state.
    Type: Grant
    Filed: April 11, 2001
    Date of Patent: December 10, 2002
    Assignee: Hewlett-Packard Company
    Inventors: Justin Allan Coppin, Jonathan P Lotz
  • Patent number: 6489809
    Abstract: A receiver circuit includes a first circuit having two modes of operation controlled by a feedback loop. The feedback loop is connected to an output of the first circuit, and the modes of operation include a first mode having a quicker response to an input falling signal edge than a second mode and a second mode with a quicker response to an input rising signal edge than the first mode. A driver stage is integrated into the first circuit to favor the rising edge or the falling edge in accordance with a control signal provided by the feedback loop.
    Type: Grant
    Filed: November 30, 2000
    Date of Patent: December 3, 2002
    Assignee: Infineon Technologies AG
    Inventor: Oliver Kiehl
  • Patent number: 6489803
    Abstract: A loss of signal condition is evaluated for an input data stream according to a signal strength threshold level. The signal strength threshold level is determined according to a supplied loss of signal (LOS) threshold level. Two hysteresis modes are used to ensure the hysteresis at low LOS threshold levels is sufficient. The first mode uses hysteresis for the signal strength threshold level that is proportional to the LOS threshold level when the LOS threshold level is above a predetermined level. The second mode employs fixed hysteresis for the signal strength threshold level when the LOS threshold level is below the predetermined level. The hysteresis provides a signal strength threshold level that has a greater magnitude on deassertion of a loss of signal indication than on assertion of the loss of signal indication.
    Type: Grant
    Filed: September 7, 2001
    Date of Patent: December 3, 2002
    Assignee: Silicon Laboratories, Inc.
    Inventors: Philip David Steiner, Gerard Pepenella
  • Patent number: 6489804
    Abstract: Programmable logic structures include logic blocks that operate at very low supply voltages. According to the invention, a pass transistor is positioned between logic blocks. Since the logic blocks of the invention operate at very low supply voltages, the pass transistor can be overdriven on, thereby reducing the added resistance. In one embodiment of the invention, the pass transistor is a low threshold transistor. In this embodiment, the pass transistor is also overdriven off to reduce leakage current and further isolate the logic blocks.
    Type: Grant
    Filed: June 1, 2001
    Date of Patent: December 3, 2002
    Assignee: Sun Microsystems, Inc.
    Inventor: James B. Burr
  • Patent number: 6486756
    Abstract: A superconductor signal amplifier which receives an extremely small high-frequency signal having a frequency of tens of GHz generated in a superconductive circuit, amplifies the voltage of the high-frequency signal without a decrease in frequency, and outputs the thus amplified high-frequency signal from the superconductive circuit. At an output part of a single flux quantum circuit using a flux quantum as a binary information carrier, there are provided a superconductive junction line for flux quantum transmission and a splitter for simultaneously producing two flux quanta from a flux quantum. According to the number of plural series-connected SQUIDs, a plurality of flux quantum signals are generated and input to the plural series-connected SQUIDs so that the SQUIDs are simultaneously switched to a voltage state. In each SQUID pair comprising two SQUIDs, a part of an inductor is shared by the two SQUIDs for reduction in inductance, thereby increasing an output voltage of the series-connected SQUIDs.
    Type: Grant
    Filed: March 26, 2001
    Date of Patent: November 26, 2002
    Assignees: Hitachi, Ltd., International Superconductivity Technology Center
    Inventors: Yoshinobu Tarutani, Kazuo Saitoh, Kazumasa Takagi, Yoshihisa Soutome, Tokuumi Fukazawa, Akira Tsukamoto
  • Patent number: 6486755
    Abstract: A vertical transition device for differential stripline paths, connects differential microstrip paths on a horizontal plane with differential triplate paths on another horizontal plane in a multilayered architecture. The differential microstrip paths include a pair of differential microstrip lines. The differential triplate paths include a pair of triplate lines. The differential microstrip lines are connected with the differential triplate lines by via-holes within the transition device, respectively.
    Type: Grant
    Filed: June 18, 2001
    Date of Patent: November 26, 2002
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventor: Hiroshi Aruga
  • Patent number: 6486705
    Abstract: Fractional cycle stealing units are introduced in the routing of a programmable device such as an FPGA or FPSC to increase system performance resulting from the particular clock routing. The disclosed fractional cycle stealing units enable given amounts of clock skew between individual distribution sinks, and/or between logic paths that are in series. Each of the delay elements ‘steals’ a portion of a clock cycle (and perhaps one or more full clock cycles) from subsequent circuits to provide a more reliable logical function, and to avoid the need for overall additional clock cycles. These fractional cycle stealing elements offer a signal skew adjustment at the sinks of the distribution with no additional routing congestion expense. The disclosed cycle stealing delay elements are programmable, and enable clock skew between individual distribution sinks.
    Type: Grant
    Filed: May 25, 2001
    Date of Patent: November 26, 2002
    Assignee: Lattice Semiconductor Corporation
    Inventors: William B. Andrews, Alfred E. Dunlop, John P. Fishburn, Harold N. Scholz
  • Patent number: 6486699
    Abstract: The invention relates to a compensation circuit for driver circuits having a current reference source which generates at least one reference signal which is modulated with respect to an input signal, having a current-comparison source which generates at least one comparison signal which is modulated with respect to the input signal, the modulated comparison signals having an inverse characteristic to that of the modulated reference signals in respect of the parameters to be modulated, having a comparison unit to which the modulated reference signals and the modulated comparison signals are fed and which generates from a comparison of these modulated modulating signals at least one digital output signal which can be fed to driver circuits connected downstream.
    Type: Grant
    Filed: December 19, 2001
    Date of Patent: November 26, 2002
    Assignee: Infineon Technologies AG
    Inventors: Dirk Friebe, Anthony Sanders
  • Patent number: 6483342
    Abstract: An embedded system bus is woven between a plurality of embedded master elements and at least one slave element within the FPGA device, and provides an external processor interface allowing direct access to any of the plurality of embedded slave elements. Using the embedded system bus, any of a plurality of masters may be allowed to program an embedded element, e.g., embedded FPGA logic, whereas conventional FPGAs allowed only a single master (e.g., a processor) to program the embedded FPGA logic. The embedded system bus is a group of signals, typically data, address and control, that connects system elements together and provides a basic protocol for the flow of data. The embedded system bus allows for control, configuration and status determination of the FPGA device. The embedded system bus is preferably a dedicated function available at all times for arbitrated access to allow communication between the various embedded system components.
    Type: Grant
    Filed: May 25, 2001
    Date of Patent: November 19, 2002
    Assignee: Lattice Semiconductor Corporation
    Inventors: Barry K. Britton, Ravikumar Charath, Zheng Chen, James F. Hoff, Cort D. Lansenderfer, Don McCarley, Richard G. Stuby, Jr., Ju-Yuan D. Yang
  • Patent number: 6483341
    Abstract: An apparatus for regulating resonance in a micro-chip has been developed. The method includes connecting a de-coupled capacitance across the supply and ground voltages, and connecting a band-pass shunt regulator that is in parallel to the capacitor across the supply and ground voltages. The regulator will short circuit the supply and ground voltages at a pre-determined frequency to reduce the resonance effect on the micro-chip.
    Type: Grant
    Filed: January 4, 2001
    Date of Patent: November 19, 2002
    Assignee: Sun Microsystems, Inc.
    Inventors: Claude R. Gauthier, Tyler J. Thorp, Richard L. Wheeler, Brian Amick
  • Patent number: 6483348
    Abstract: Current pulse matchers monitor the wires of a static or precharge-pulldown bus. Each current pulse matcher monitors the wire that it is connected to. For a precharge-pulldown bus, if the wire has been discharged during the pulldown cycle of the bus, the precharge current pulse matcher does not consume any current. If, however, the wire was not discharged during the pulldown cycle of the bus, then the precharge current pulse matcher consumes an amount of current that approximates the amount of current used to precharge that wire had it been discharged. For a static bus, the current pulse matcher does not shunt current if the wire has not just made transition. Otherwise, the static bus current pulse matcher shunts an amount of current that may approximate the amount of current used to transition the bus signal from one logic state to another.
    Type: Grant
    Filed: October 24, 2000
    Date of Patent: November 19, 2002
    Assignee: Hewlett-Packard Company
    Inventor: Samuel D. Naffziger
  • Patent number: 6483349
    Abstract: Differential amplifier circuits that receive input signals fed through external terminals are served with a first operation voltage and a second operation voltage through a first switching MOSFET and a second switching MOSFET, said first and second switching MOSFETs are turned on by a bis voltage-generating circuit when said input signal is near a central voltage of said first and second operation voltages, control voltages are formed to turn either said first switching MOSFET or said second switching MOSFET on and to turn the other one off to produce a corresponding output signal when the input signal continuously assumes said first voltage or said second voltage for a predetermined period of time, thereby to supply an input signal of a first amplitude corresponding to said first operation voltage and said second operation voltage as well as an input signal of a second amplitude corresponding to a predetermined intermediate voltage between said first operation voltage and said second operation voltage.
    Type: Grant
    Filed: November 15, 2001
    Date of Patent: November 19, 2002
    Assignees: Hitachi, Ltd., Hitachi ULSI Systems Co., Ltd.
    Inventors: Takeshi Sakata, Hitoshi Tanaka, Osamu Nagashima, Masafumi Ohi, Sadayuki Morita
  • Patent number: 6483346
    Abstract: Failsafe interface circuits are provided for an integrated circuit having a core logic section providing a signal to, or receiving a signal from, a bond pad connection. The interface circuits employ high voltage tolerant, extended drain devices in circuit arrangements which insure that the stress of a failsafe event is only exhibited by the extended drain devices. A failsafe event is defined as a bond pad voltage which exceeds the supply voltage of the integrated circuit plus the threshold voltage of the transistors within the integrated circuit. Both failsafe output driver circuit and failsafe receiver circuit embodiments are provided.
    Type: Grant
    Filed: January 25, 2002
    Date of Patent: November 19, 2002
    Assignee: Texas Instruments Incorporated
    Inventors: Keith E. Kunz, James D. Huffman
  • Patent number: 6480024
    Abstract: A circuit configuration includes two signal path sections that are used to program the delay of a signal path, in particular in DRAMs. The two signal path sections have different delays and can be driven in parallel at the input end. The two signal path sections can be connected to an output terminal via a multiplexer. A selection circuit includes two signal path sections which are connected between supply voltage potentials. The selection circuit has two complimentary transistors which are connected in series and has source-end programmable elements. These transistors can be driven by complimentary control signals. This permits the delay to be programmed flexibly with little expenditure on circuitry.
    Type: Grant
    Filed: October 19, 2001
    Date of Patent: November 12, 2002
    Assignee: Infineon Technologies AG
    Inventors: Stefan Dietrich, Thomas Hein, Patrick Heyne, Michael Markert, Thilo Marx, Torsten Partsch, Sabine Schöniger Kieser, Peter Schrögmeier, Michael Sommer, Christian Weis