Patents Examined by Don Phu Le
  • Patent number: 6448813
    Abstract: An output driver circuit for driving a signal onto a signal line. The output driver circuit comprises at least one driver circuit and a passive network. The passive network is configured to limit the variation in the output impedance of the output driver circuit. The output driver circuit thus provides an output impedance that closely matches the loaded impedance of the signal line at all times so as to minimize secondary reflections on the signal line.
    Type: Grant
    Filed: March 6, 2001
    Date of Patent: September 10, 2002
    Assignee: Rambus Inc.
    Inventors: Bruno Werner Garlepp, Kevin S. Donnelly, Jared LeVan Zerbe
  • Patent number: 6448811
    Abstract: A current reference with reduced sensitivity to process variations includes a variable resistor and a control transistor. The control transistor has a generated current from source-to-drain that first passes through the variable resistor. The control transistor has a reference voltage applied to the gate, and the source-to-gate voltage is a function of the reference voltage and the voltage drop across the variable resistor. A control loop circuit measures the generated current and modifies the resistance value of the variable resistor in response. An external precision resistor is used to measure the generated current, and current variations as a result of process variations are reduced.
    Type: Grant
    Filed: April 2, 2001
    Date of Patent: September 10, 2002
    Assignee: Intel Corporation
    Inventors: Siva G. Narendra, Amaresh Pangal, Stephen R. Mooney
  • Patent number: 6445210
    Abstract: In a level shifter including a latch consisting of two p-channel transistors P1 and P2, when an input signal at a terminal IN changes from H- into L-level, an n-channel transistor N2 turns ON, thereby dropping a potential level at a node W2. However, since a p-channel transistor P4 is OFF, no short-circuit current flows from a high voltage supply VDD3 into the ground by way of the transistors P2 and N2. On the other hand, since n- and p-channel transistors N1 and P3 are OFF, both terminals of a node W1 are electrically isolated. But the high voltage supply VDD3 pulls the node W1 up to a high voltage level by way of the p-channel transistors P4 and P1 and another p-channel transistor P5 as a resistor. Accordingly, the capacitance to be driven by the n-channel transistors N1 and N2 can be reduced, thus shortening the delay.
    Type: Grant
    Filed: February 7, 2001
    Date of Patent: September 3, 2002
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventor: Naoki Nojiri
  • Patent number: 6445213
    Abstract: The present invention is a dynamic logic propagation delay targeting tool that includes a gate target delay initializer 90, a levelizer 82, a backward logic scanner 94, a forward logic scanner 96, a gate target delay incrementor 97, and a gate target delay comparator 97 that together calculates the propagation delay of a signal in a specified block of dynamic logic.
    Type: Grant
    Filed: April 27, 2001
    Date of Patent: September 3, 2002
    Assignee: Intrinsity, Inc.
    Inventors: Gopal Vijayan, James S. Blomgren, Donald W. Glowka, Stephen C. Horne
  • Patent number: 6441640
    Abstract: A circuit for regulating resonance in a micro-chip has been developed. The circuit includes micro-chip supply voltage and a ground voltage, and a band-pass shunt regulator that is in parallel to the capacitor across the supply and ground voltages. The regulator will short circuit the supply and ground voltages at a pre-determined frequency to reduce the resonance effect on the micro-chip.
    Type: Grant
    Filed: January 4, 2001
    Date of Patent: August 27, 2002
    Assignee: Sun Microsystems, Inc.
    Inventors: Claude R. Gauthier, Brian Amick, Tyler J. Thorp, Richard L. Wheeler
  • Patent number: 6441645
    Abstract: A bipolar drive circuit comprises a differential or single-ended current mirror with signal inputs and outputs connected via resistors to a low voltage supply, e.g. 1.5 volts. A signal output voltage swing is determined and stabilized by a compensation circuit comprising a transistor having a base supplied with a reference voltage, a collector coupled via a resistor to the low voltage supply, and an emitter coupled via a resistor to ground, and a current mirror having an input coupled to the collector of the transistor and a current mirror output coupled to each signal input. A plurality of current mirror circuits can be connected in cascade, and the signal output voltage swing of each current mirror circuit can be similarly determined. The arrangement facilitates providing a drive circuit with high frequency, low supply voltage, and low power operation without transistor saturation.
    Type: Grant
    Filed: March 27, 2001
    Date of Patent: August 27, 2002
    Assignee: Nortel Networks Limited
    Inventor: Stepan Iliasevitch
  • Patent number: 6433578
    Abstract: A heterogeneous programmable gate array has an unstructured logic sub-array and a structured logic sub-array. An unstructured input/output interconnect structure delivers unstructured-to-unstructured input/output signals to the unstructured logic sub-array, while a bussed input/output interconnect structure delivers structured-to-structured input/output signals to the structured logic sub-array. A control signal bus is connected between the unstructured logic sub-array and the structured logic sub-array to deliver unstructured source signals therebetween. A bussed signal bus is connected between the unstructured logic sub-array and the structured logic sub-array to deliver structured source signals therebetween.
    Type: Grant
    Filed: May 5, 2000
    Date of Patent: August 13, 2002
    Assignee: Morphics Technology, Inc.
    Inventor: Stephen L. Wasson
  • Patent number: 6433580
    Abstract: An architecture and distributed hierarchical interconnect scheme for field programmable gate arrays (FPGAs). The FPGA is comprised of a number of cells which perform logical functions on input signals. Programmable intraconnections provide connectability between each output of a cell belonging to a logical cluster to at least one input of each of the other cells belonging to that logical cluster. A set of programmable block connectors are used to provide connectability between logical clusters of cells and accessibility to the hierarchical routing network. An uniformly distributed first layer of routing network lines is used to provide connections amongst sets of block connectors. An uniformly distributed second layer of routing network lines is implemented to provide connectability between different first layers of routing network lines. Switching networks are used to provide connectability between the block connectors and routing network lines corresponding to the first layer.
    Type: Grant
    Filed: March 2, 1998
    Date of Patent: August 13, 2002
    Assignee: BTR, Inc.
    Inventor: Benjamin S. Ting
  • Patent number: 6433576
    Abstract: A circuit for altering a chip pad signal incorporates a primary driver that is configured to deliver a chip pad signal to an IC package. The circuit also is configured to cooperate with a second signal and a third signal, with the second signal having a voltage higher than the voltage of the first logic high, and the third signal having a voltage lower than the voltage of the first logic low. So configured, the primary driver may selectively deliver a second logic high, which has a voltage higher than the voltage of the first logic high, to the IC package, and may selectively deliver a second logic low, which has a voltage lower than the voltage of the first logic low, to the IC package. Electronic devices, systems and methods also are provided.
    Type: Grant
    Filed: August 3, 2001
    Date of Patent: August 13, 2002
    Assignee: Agilent Technologies, Inc.
    Inventor: Jason Harold Culler
  • Patent number: 6429678
    Abstract: An active terminating circuit has buffers to produce wider voltage drives on clamping transistors. A transmission line drives coupling capacitors. One capacitor drives an upper node that drives the gate of an upper buffer transistor. The upper buffer transistor drives a p-gate node coupled to a gate of a p-channel clamping transistor. The other capacitor drives a lower node that drives the gate of a lower buffer transistor, which drives an n-gate node of an n-channel clamping transistor. The drains of the clamping transistors are connected to the transmission line. Resistors pull the lower node to the power-supply voltage and pull the upper node to ground when no transitions occur on the transmission line, achieving zero standby power. When a transition is detected, it is coupled through the capacitors and buffered to the p-gate and n-gate nodes. Limiting transistors limit upper and lower node swings.
    Type: Grant
    Filed: November 21, 2001
    Date of Patent: August 6, 2002
    Assignee: Pericom Semiconductor Corp.
    Inventors: Anthony Yap Wong, Kwong Shing Lin
  • Patent number: 6429686
    Abstract: An output driver on an integrated circuit (IC) includes at least one transistor that has a thicker gate oxide than other standard transistors in the IC. In one embodiment, the output driver includes two pull-up transistors. A first pull-up transistor has a thicker gate oxide than standard transistors on the IC to provide a wide range of output voltages on the pad. A second pull-up transistor has a standard, i.e. thin, gate oxide thickness to ensure a fast low-to-high voltage transition on the pad. The other transistors in the output driver have standard gate oxide thicknesses. Illustrative thicknesses include 150 Angstroms for the first pull-up transistor and 50 Angstroms for the second pull-up transistor.
    Type: Grant
    Filed: June 16, 2000
    Date of Patent: August 6, 2002
    Assignee: Xilinx, Inc.
    Inventor: Hy V. Nguyen
  • Patent number: 6429685
    Abstract: An integrated circuit (100, 200, 300) includes a voltage-mode driver circuit having an analog on-chip termination and also having a substantially constant output impedance across an operating range of an output voltage of the voltage-mode driver circuit. The voltage-mode driver circuit also has slew rate control of the output voltage.
    Type: Grant
    Filed: November 13, 2000
    Date of Patent: August 6, 2002
    Assignee: Gain Technology Corporation
    Inventor: Troy L. Stockstad
  • Patent number: 6429684
    Abstract: A body-tied-to-drain transistor having significantly reduced gate delay and being particularly appropriate for large drivers where a series of inverters is used. The basic configuration ties the drain of the transistor to the body of the transistor when the transistor is turned on, and is disconnected when the transistor is turned off.
    Type: Grant
    Filed: September 29, 1998
    Date of Patent: August 6, 2002
    Assignee: Texas Instruments Incorporated
    Inventor: Theodore W. Houston
  • Patent number: 6426646
    Abstract: An ECL terminating circuit, in which it is prevented that the amplitude of an output signal from an ECL outputting circuit or a PECL outputting circuit is lowered caused by that the supply voltage for the circuit has been lowered, and also it is prevented that the waveform of the output signal is deteriorated caused by that the distance of a transmission line where the output signal being high speed is transmitted is made to be long, is provided. The ECL terminating circuit consists of a PECL outputting circuit, a resistor, a transmission line, a load circuit, and a terminal element. And the terminal element is connected to the resistor in series and the resistance value of the terminal element is about 0 &OHgr; at a direct current (DC), but is made to be large at an alternating current (AC).
    Type: Grant
    Filed: May 9, 2001
    Date of Patent: July 30, 2002
    Assignee: NEC Corporation
    Inventors: Munetoshi Yoshizawa, Masashi Tachigori
  • Patent number: 6426654
    Abstract: Disclosed herein is a dynamic type circuit which transmits a signal between relatively long-distant circuit blocks lying within a semiconductor integrated circuit chip. A whole signal path thereof comprises a plurality of sections. A section formed by a first type of signal line, which is precharged to a high level and to which a decision as to whether it is driven to a low level according to a signal inputted from a preceding section or it is left in floating state, is made, and a section formed by a second type of signal line, which is precharged to a low level in reverse and to which a decision as to whether it is driven to a high level according to a signal inputted from a preceding section or it is left in a floating state, is made, exist in alternate shifts. The respective sections are respectively connected to preceding-stage sections through MOS transistors for driving signal lines for the sections.
    Type: Grant
    Filed: December 13, 2000
    Date of Patent: July 30, 2002
    Assignee: Hitachi, Ltd.
    Inventor: Noboru Masuda
  • Patent number: 6424171
    Abstract: A programmable logic LSI resolves a problem leaving some wiring resource extra upon realizing one circuit (some wiring cells are not used) and leaving some logical resource extra upon realizing another circuit (some logical cell are not used, and can realize both functions of logical resource and wiring resource with a single base cell. The base call for a programmable logic LSI which is formed by connecting a plurality of the base cells, includes a combined programmable circuit realizing a programmable logic circuit function and a programmable wiring circuit function, and a mode setting circuit for selectively making one of the programmable logic circuit function and the programmable wiring circuit function according to a mode information. Upon functioning as the programmable logic circuit, logical operation is performed with respect to an input signal input to the base cell to feed an output signal.
    Type: Grant
    Filed: October 28, 1999
    Date of Patent: July 23, 2002
    Assignee: NEC Corporation
    Inventors: Masato Motomura, Taro Fujii, Koichiro Furuta
  • Patent number: 6424174
    Abstract: Disclosed is a static CMOS circuit having an input and an output, comprising: a pass gate switch fabricated from thick oxide devices coupled between the input and a fast CMOS circuit fabricated from thin oxide devices, the fast CMOS circuit coupled to the output; and a slow CMOS circuit fabricated from thick oxide devices coupled between the input and the output.
    Type: Grant
    Filed: October 17, 2001
    Date of Patent: July 23, 2002
    Assignee: International Business Machines Corporation
    Inventors: Edward J. Nowak, Minh H. Tong
  • Patent number: 6424179
    Abstract: The present invention provides a logic unit and integrated circuit for clearing interrupts. The logic unit is coupled to a bus operating in a first clock domain, and is arranged to interface between the bus and a device operating in a second clock domain, the frequency of the second clock domain being less than the frequency of the first clock domain. In accordance with the present invention, the logic unit comprises an interrupt source, responsive to a signal issued by the device, to assert a first interrupt signal in the second clock domain, and output logic, responsive to the first interrupt signal-to output a second interrupt signal via the bus to a processor operating in the first clock domain. The processor is arranged to process the interrupt indicated by the second interrupt signal, and to issue a clear request signal at a predetermined point during processing of the interrupt.
    Type: Grant
    Filed: February 21, 2001
    Date of Patent: July 23, 2002
    Assignee: Arm Limited
    Inventor: Ashley Miles Stevens
  • Patent number: 6420904
    Abstract: The precharge of a domino logic stage is controlled based on the precharge delay of a prior domino logic stage. The precharge of the logic stage does not occur until the output of the prior logic stage corresponds to the precharge logic state. Because the precharge logic state output of a preceding stage is an inactive state of a subsequent logic stage, the logic function of the subsequent logic stage is in a non-conducting state when the output of the prior logic stage is in the precharge logic state. By providing the precharge to a subsequent stage-only after the output of the prior stage is in the precharge state, there can be no DC current flow during the precharge of the subsequent stage, and the need for an evaluation transistor to block the DC current flow during precharge is eliminated.
    Type: Grant
    Filed: January 25, 2001
    Date of Patent: July 16, 2002
    Assignee: Koninklijke Philips Electronics N.V.
    Inventors: Santanu Dutta, Deepak Singh
  • Patent number: 6420906
    Abstract: An OR circuit allowing one stable output voltage from a plurality of input voltages is disclosed. A first FET is connected between a corresponding input terminal and an output terminal in such a manner that an inherent diode of the FET is connected in a forward direction. A second FET is connected between a corresponding input terminal and the output terminal in the same manner as the first FET. Each of the input voltages is compared with the output voltage. The conduction/non-conduction states of each of the first and second FETs are independently controlled depending on the comparison result.
    Type: Grant
    Filed: March 22, 2001
    Date of Patent: July 16, 2002
    Assignee: Allied Telesis Kabushiki Kaisha
    Inventor: Yoshimi Kohda