Abstract: According to the present invention, a large compensation effect can be obtained in a small operation volume regardless of which one of a distortion due to a frequency selective fading and a distortion due to an interference of adjacent waves is ruling. In the present invention, a principal wave signal and signals of channels adjacent to both sides of said principal wave are taken out, and power of these signals is compared to select either one of the fractional interval equalizer and the linear decision feedback equalizer.

Abstract: A system for RF communications utilizing an open architecture bus line is disclosed. The system consists of a single-board receiver exciter, a single-board modulator and a system control processor all interfaced to a standard bus line. All three units are implemented on single-board assemblies and are programmable to perform over a variety of frequency ranges, to operate at one of a variety of modulating schemes, and to utilize varying data rates.

Abstract: In a cross polarization interference canceller for use in digital radio communications, a signal processing circuit monitors whether numbers of word sync signals and error pulses obtained in error correction decoding exceed specified values, and outputs reset signal RS1 when an abnormality is detected. A signal level detection circuit outputs reset signal RS2 when it is detected that a level of a different polarization side baseband signal from a demodulator is lower than specified. A logical sum RS3 of reset signals RS1 and RS2 is supplied to a cross polarization interference cancellation device, which may have a transversal filter. When the word is not synchronized or the number of error pulses generated in error correcting decoding exceeds the specified value, the self-polarization side can be protected from unnecessary interference and disturbance and the self-polarization side data can be protected from disturbance even though an abrupt abnormality occurs in different polarization signals.

Abstract: A data receiving apparatus capable of correctly obtaining decoded data of a received signal even if the center frequency of the received signal has a frequency shift and the state of transmission line changes with time. The coefficient of an equalizer is calculated basing upon an error signal obtained from the received signal and a shift of the center frequency obtained from the error signal. The coefficient is renewed each time a new received signal is supplied.

Abstract: A synchronization control circuit applicable to a TDMA (Time Division Multiple Access) digital mobile communication system for controlling the transmission and reception time base of a mobile station on which the circuit is mounted. The synchronization control circuit includes a plurality of time base counter circuits each counting down standard clock pulses to generate a plurality of timing pulse sequences having time bases which are respectively associated with the cells of the system. All the time base counter circuits share a single counter controller which controls the writing and reading of counts out of the time base counter circuits. The counter controller selectively produces the outputs of one of the time base counter circuits as a timing pulse sequence. The synchronization control circuit, therefore, is small size and light weight and saves power.

Abstract: Formatted serial synchronous character data is converted to serial asynchronous data, where the synchronous bit rate varies from the asynchronous intracharacter bit rate. The character data utilizes a start bit-stop bit format which enables the converter to insert stop bits occasionally in proportion to the bit rate difference, thus compensating for bit rate mismatch. The converter offers programmable character lengths of 7, 8, or 9 bits and a possible seven different asynchronous bit rates, each selected by three programmable selection inputs. In addition, the invention uses a total digital design architecture enabling gate array integrated circuit implementation.

Abstract: A bidirectional radio system for low cost, high through-put accumulation of data from a large number of site units. The site units are connected to remote radio transceivers in radio communication with a plurality of base stations. Accurate frequency synchronization allows multiple carriers within a 12.5 kHz FCC bandwidth. Frequency synchronization is achieved at low cost by transmitting a high accuracy carrier and clock signal at a base station, and using receiving circuitry a remote stations to extract the base clock signal and base carrier frequency and a phase-lock loop to stabilize the remote station carriers. The reception circuitry at a remote station provides independent carrier frequency and clock rate recovery, a phase-lock loop at baseband, and a coarse clock rate recovery circuit coupled to a fine clock rate recovery circuit. Remote station responses are time domain multiplexed.

Abstract: A bias voltage for a VCO is generated by monitoring UP and DOWN control signals from a charge pump and generating first and second output signals upon detecting a predetermined number of consecutive UP pulses or DOWN pulses. The first output signal causes a shift register pre-loaded with a data pattern having one odd logic state to shift one bit location to left, while the second output signal moves the odd logic state one bit location to the right. The bias voltage to the VCO is selected based on the odd logic state bit location. Any variation in VCO output frequency due to intermittent ground bounce is eliminated by requiring a consecutive number of UP pulses or DOWN pulses before moving the VCO bias point.

Abstract: A digital clock reconstruction circuit comprising a first flip flop, a programmable delay chain, and a first assembly of gates is provided to digitally compensate an entering digital clock's skew for a high speed digital circuit by digitally reconstructing the entering clock. The reconstructed clock will also provide the minimum amount of high and low time in a period required by the components of the high speed circuit. Additionally, at least one measurement or comparison circuit is provided for measuring the frequencies of the reconstructed clock under various delay settings of the programmable delay chain to calibrate the digital clock reconstruction circuit. Under the calibration process of the present invention, the delay setting is determined iteratively, starting from an initial setting and varying the delay setting in a predetermined manner.

Abstract: A .pi./4 shift QPSK modulator includes a pre-processing part for subjecting an input transmitting code sequece to a pre-processing, a modulator part for selectively subjecting the transmitting code sequence received via the pre-processing part to a modulation in conformance with QPSK and a modulation in conformance with a .pi./4 shift QPSK, and an output part for outputting a modulated signal having a burst form based on an output of the modulator part depending on a burst signal having leading and trailing edges, where the pre-processing part carries out the pre-processing so that I-axis and Q-axis data supplied to the modulator part have the same symbol in succession at parts corresponding to the leading and trailing edges of the burst signal, so as to suppress generation of unwanted waves in the output part.

Abstract: A data interfacing system for asynchronous data which has a predetermined data format and receives a data group transmitted in an asynchronous manner, uses a predetermined basic clock signal in providing synchronism to asynchronous data group. The system generates a line recognizing signal corresponding to each data line in the particular format of the data group, generates a line clock signal having a predetermined pulse at the end point of each data line in response to the line recognizing signal and the basic clock signal. The system also generates a pulse signal having a period corresponding to a single data bit of the data group by counting the basic clock signal during a data bit section enabled by the line recognizing signal. The data is fed to a shift register permitting particular data to be extracted synchronously from the data group. A corresponding data interfacing method is also described.

Abstract: Method and apparatus for controlling a PLL so that handover between fine and coarse loops take place at 2.5% of the nominal VCO frequency and where the coarse and fine loops error are combined in a summer circuit which employs a series circuit having a P-channel and N-channel FET with common drains and where the drains connected to the summer output node.

Abstract: A quadrature amplitude modulation (QAM) communication system is provided in which data can be communicated in any one of a plurality of QAM modes, such as 16-QAM, 32-QAM, and 64-QAM. A receiver detects the particular QAM mode transmitted on a trial and error basis, by attempting to decode the received data using different QAM modes until a synchronization condition is detected. The synchronization condition can require that a plurality of different synchronization tests be met. In a specific embodiment, a first synchronization test is met when a renormalization rate of a trellis decoder is below a threshold value. A second synchronization test is met when a first synchronization word is detected in the received data. A third and final synchronization test is met when a second synchronization word is detected in the received data. In order to reduce the cost of the receiver, most of the QAM mode dependent components are implemented using look-up tables stored in PROMs.

Abstract: A serial interface bus system for transmitting and receiving a plurality of bus signals which collectively allow communication of data between a digital audio source (12, 22, 24, 26, 56, 82) such as a compact disc and a digital sink (42, 52, 62, 64, 66) such as a digital signal processor. The plurality of bus signals provided by the interface bus system allow many different audio sources and sinks to be used without glue logic. The plurality of bus signals allow multiple transceivers to be configured in a daisy chain (20, 60) wherein a master is selectively chosen to optimize performance of such a system. The daisy chain configuration may be implemented to provide digital data to a wide variety of storage circuits for digital information.

Abstract: A repeater station comprises an RFD frame synchronization circuit, an AND gate, and an IFD frame synchronization circuit. The RFD frame synchronization circuit outputs a frame synchronization signal indicating the timing of an auxiliary signal by performing frame synchronization with regard to the RFD. The AND gate inhibits clock signals during periods of the auxiliary signals and allows the clock signals to pass through during the other periods. The IFD frame synchronization circuit performs frame synchronization of the RFD with regard to the IFD by carrying out frame synchronization operation in accordance with the clock signals output from the AND gate. The IFD are accessible in the above simple construction.

Abstract: An input clock signal associated with an input data signal is divided by a predetermined integer N, to form a sub-rate clock signal. The sub-rate clock signal is sampled and transmitted along with the input data over an asynchronous data channel. At the receiver, the resulting sub-rate clock signal is received and coupled to a phase lock loop which generates a recovered clock signal of the same frequency and substantially in phase with the input clock signal.

Abstract: Timing recovery circuitry for recovering digital data generates a timing signal which is a function of the delay provided by an equalizer to one or more predetermined frequency components of its input signal. Advantageously, this approach is applicable to systems which utilize one or more baseband or passband equalizers. The disclosed embodiments of the present invention pertain to a dual-duplex system. In such a system, the digital data to be transmitted is divided into two different digital signals and each signal is coupled through an associated transmission channel. At the receiver, the received version of each transmitted signal is processed by an associated equalizer and the outputs therefrom are combined to recover the digital data. In the disclosed embodiments of the present invention, the necessary timing signal for such recovery is a function of the delay introduced by each equalizer to at least one predetermined frequency component of that equalizer's input signal.

Abstract: A digital simulcast transmission is automatically aligned, at a simulcast receiver (22) that simultaneously receives a plurality of RF signals from a plurality of transmitters, each of the RF signals being modulated to convey identical digitally encoded information. An equalizer (24) adaptively equalizes the plurality of received RF signals to substantially correct for a misalignment in time between the received signals. The misalignment in time is due in part to a non-simultaneous transmission of the identical digitally encoded information from the plurality of transmitters. Equalizer embodiments include a Decision Feedback Equalizer (DFE) and an equalizer based on a Maximum Likelihood Sequence Estimator (MLSE). Embodiments of the DFE are an Order Recursive Lattice-DFE and a Fast Kalman DFE.

Abstract: A frequency-shift keying (FSK) signal detector splits an FSK signal into two paths. In one path, a phase-altering circuit having a variable frequency characteristic between the two encoding frequencies of the FSK signal provides either a phase lead or a phase lag depending upon the instantaneous frequency of the FSK signal. The phase-altered signal is sampled in response to the signal in the second path to decode a digital signal.

Abstract: The present invention comprises a method and apparatus for selecting one of at least two antennas (202, 204) in a communication unit (102) for use in a wireless communication system (100). A signal is received by a radio frequency receiver (208) during a receiving period from one of the at least two antennas (202, 204) currently selected by an antenna switch (206), the signal transmitted in a digital communications format comprising a plurality of valid data patterns and having an invalid data pattern that is not transmitted. The number of data patterns in the signal received that comprise the invalid data pattern is determined by an antenna diversity control circuit (222), and for a subsequent receiving period one of the at least two antennas (202, 204) is selected based upon the number of occurrences of the invalid data pattern determined.