Abstract: For use with a quartz angular rate sensor, a frequency and phase-locked synthesizer recovers a reference signal virtually free of phase noise, and generates a quadrature-phase reference signal for complex demodulation of the angular rate signal. The synthesizer also ensures a precisely adjusted phase shift of approximately zero across the drive tines of the sensor. Moreover, the digital synthesizer provides a precise numerical indication of the drive frequency, which can be used for compensation and automatic tuning of filters, such as a tracking filter, a filter in an automatic gain control, and notch filters in the phase and/or frequency detectors in the digital synthesizer. The tracking filter is used as a pre-filter for the synthesizer, and is responsive to a passband-width control signal generated from the magnitude of the frequency and phase error signal controlling the frequency generated by the synthesizer.

Abstract: A sliding correlator for initial synchronization and tracking of a SS (Spread Spectrum)-modulated signal containing a transmitted pseudo noise (PN) code, digitizes the received signal, and attempts to correlate the PN code in the received signal with a locally generated reference PN code. Initial synchronization employs correlation with three reference PN codes, an early, center and late channel. When correlation is found between the transmitted PN code and one of the reference PN codes, the three reference PN codes are shifted to align the center channel with the correlated channel and to displace the early and late channel reference PN codes to one side and the other of the center channel. In one embodiment, the displacement is one-third chip, and in another embodiment, the displacement is one-half chip.

Abstract: A data communications system comprising first (B), second (C) and third (A) remote units arranged for communication over a common communications channel. A first message to be sent to the second unit (C) is generated at the first unit (B). The first unit (B) waits for the channel to become available for independent transmission of the message. If (t.sub.0), before the channel becomes available for independent transmission, a new message is received from the third unit (A) requiring an acknowledgement, the new message is received from the third unit (A), an acknowledgement of receipt of the message is transmitted (t.sub.1) and in a substantially continuous transmission (t.sub.2), the first message to the second unit is transmitted in a "piggy-back" manner. In a preferred arrangement, multiple messages can be piggy-backed to different units. Priorities can be assigned to these messages for acknowledgements.

Abstract: In a noise cancel circuit for cancelling leading and travelling noises from an input pulse signal comprising a sequence of input pulses each of which is defined by a predetermined input pulse period and a predetermined input pulse width, a leading noise cancel circuit cancels the leading noise from the input pulse signal and produces a leading noise cancelled signal. A trailing noise cancel circuit cancels the trailing noise from the leading noise cancelled signal and produces a trailing noise cancelled signal. Thus, the noise cancel circuit produces an output pulse signal comprising a sequence of output pulses each of which is defined by an output pulse period equal to the predetermined input pulse period and an output pulse width equal to the predetermined input pulse width.

Abstract: A technique for reliable passage of handshaking information between a cellular modem and a land modem. Instead of bare transmission over a voice channel connection highly susceptible to signal fading and dropout, the initial modem handshaking exchange is instead FSK-encoded and broadcast using a network data signalling methodology already used to reliably pass signalling information between the base and registered mobiles. Automatic retransmission request signalling and transmission redundancy may be implemented to insure successful receipt at the receiving end of the radio link. Once received and verified, handshaking information is decoded and delivered to the destination modem in the appropriate format along cleaner fixed pathways. Reliable handshaking operations are contemplated whether the destination modem is a cellular modem registered in auto-answer mode (land-originated data call), or a land modem (mobile-originated data call).

Abstract: A digital audio signal demodulator which demodulates an input digital audio interface format signal inputted with asynchronous serial bits to a non-return to zero (NRZ) signal, corrects error per frame, and provides the error-corrected NRZ signal, being synchronized with a digital-to-analog conversion control signal. According to the demodulator, data in the digital audio interface format signal except a header region is demodulated in a demodulating section and the demodulated NRZ data is converted into parallel NRZ data by a serial-parallel conversion section. The even parity error of the parallel NRZ data is corrected in accordance with error check pulses from an error detecting and latch section, and the error-corrected parallel NRZ data is converted into serial data by a parallel-serial conversion section to be provided to a following digital-to-analog converter.

Abstract: A communication system is simpler and conserves power by eliminating the need for a reference frequency oscillator in the transmitter circuit. In a battery operated transceiver of the present invention, the receiver portion includes a tracking oscillator. The tracking oscillator output is used to synchronize received data and as a reference frequency source for the transmitter. In a half duplex communication system a reply signal is transmitted while no command signal is being received. Therefore, the transceiver in such a system includes circuitry for maintaining the reference frequency during transmission. Thus, the frequency accuracy of the transmission is based on the frequency accuracy of the received command signal. The tracking oscillator in one embodiment includes a phase locked loop circuit having a voltage controlled oscillator (VCO), an up-down counter, and a digital to analog converter (DAC) for determining the VCO frequency.

Abstract: An automatic frequency control apparatus used in an MPSK communication system detects a frequency offset between a carrier and a local oscillation signal for adjustment of a local oscillation frequency. A phase difference detector generates a first phase difference detection signal having, as a phase value, a difference between the phases of various samples of the sampled signal. A phase altering unit generates a second phase difference detection signal having a phase value different from that of the first phase difference detection signal. A frequency offset signal generator estimates transmission phase information by using the phase value of the second phase difference detection signal and reference phase signals used for MPSK modulation, thereby generating a frequency offset signal which is determined by the transmission phase signal and the second phase difference detection signal.

Abstract: A transceiver for improving the spectral efficiency and the capacity of cellular communication systems is disclosed. The transceiver uses an antenna array for communicating in a cellular communication system with a plurality of mobile stations. In addition, the transceiver contains a spatial filter connected to an antenna array wherein the spatial filter has as many outputs as there are array elements and as many inputs as there are spatial channels. A splitter then splits data to be transmitted to each mobile station into a number of parallel data streams, the number of parallel data streams corresponds with the number of spatial channels in the system, wherein the data streams, are delayed based upon uplink measurements. Finally, power allocators are provided for allocating transmission power to each possible channel based upon long-term SNR measurements on the uplink.

Abstract: A target signal input to a mixer circuit of a frequency converter is frequency-converted to have a low frequency by a signal obtained by frequency-multiplying an output signal from the voltage-controlled crystal oscillator by M. The frequency-converted output is compared with the output signal from the voltage-controlled crystal oscillator by a phase/frequency comparator. A loop filter receives an error signal based on the phase/frequency comparison and performs loop control to lock the phase of the output signal from the voltage-controlled crystal oscillator to the phase of the output signal from the frequency converter. The jitter component of the target signal exhibiting phase variations at a frequency higher than a loop band contained in the error signal is output from a jitter detection filter before the loop filter via a branching circuit. Even if the target signal having a high frequency undergoes a great frequency change, stable, accurate jitter measurements can be performed following the change.

Abstract: An apparatus and method for varying the slew rate of a digital AGC circuit is disclosed. A gain amplifier receiving an analog signal from a tuner is converted by an A/D converter into a digital form. An ABS circuit then obtains an absolute value level of the signal, which is then low pass filtered. The filtered signal is compared to a reference level to determine if the gain should be increased or decreased. The filtered signal is also communicated to a lock detect circuit to determine how far out of the desired range the signal is, thereby requiring large step changes for a fast, coarse adjustment or smaller step changes fine adjustment of the gain. An integrator combines the two results to determine the varying slew rate of the gain signal, which is converted back to the analog domain to control the amplifier.

Abstract: This disclosure describes an apparatus for data communication from a first data bus having a first clock frequency to a second data bus having a second clock frequency, asynchronous to the first frequency. The apparatus includes a synchronizer operative to sample data on said first data bus at a selected sampling rate and to provide such data to said second data bus at selected sampling rate.

Abstract: An improved digital phase detector is used in a digital phase lock loop having a digitally controlled oscillator which includes a state controller and a counter. One embodiment of the phase detector includes a digital integrator; a first register and a first absolute value function; a second register and a second absolute value function; and a subtractor. In another embodiment the integrator includes a tapped delay line and a parallel summing network. The summing network includes a flow counter. The invention to provide a mechanism for ensuring the symmetry of the integration intervals of an early/late gate phase detector in the presence of phase error and to achieve relaxed timing for the phase error calculation without shortening the integration intervals to less than half a bit time while providing a valid phase error output once for each bit period.

Abstract: In accordance with the present invention, a technique for efficiently utilizing memory in determining which next state accumulated cost to retain, such as in a communication system or a Viterbi decoder. The system includes a memory having a portion of registers allocated to a first array and a portion of registers allocated to a second array. The technique includes retrieving a present state accumulated cost from a storage register of the first array and calculating a next state accumulated cost based on the present state accumulated cost. The next state accumulated cost is stored in a storage register of the second array. The second array is designated as containing present state accumulated costs. A present state accumulated cost is retrieved from a storage register of the second array and used in calculating a subsequent next state accumulated cost. The subsequent next state accumulated cost is stored in a storage register of the first array.

Abstract: An equalisation arrangement compensates for multipath phase and amplitude distortion effects in a transmission channel by first measuring such distortion effects as they occur over time in a calibration phase, thereby obtaining phase and amplitude compensation factors, then applying these factors to a correcting circuit situated in the signal path of the receiver at the appropriate times during a subsequent data transmission phase. Calibration is achieved by feeding a received calibration signal to an amplifier, preferably a successive detection logarithmic amplifier (26), comparing the phase of the limited linear output of the logarithmic amplifier with a delayed version of itself (30, 28), and using the amplitude information (39) in the logarithmic output (72) of the logarithmic amplifier (26) and the phase-change information (35) resulting from the phase comparison to compute the phase and amplitude compensation coefficients.

Abstract: A connecting apparatus for interconnection between serial data transmission devices, includes a DTE/DCE selector switch, a signal level converter, a single chip CMOS CPU and the RJ45 telephone bus cables, wherein the CPU controls the receiving and transmitting modes between the signal lines of the RS232 interface and the RJ45 telephone bus cables and also controls data transmission time so as to prevent the connected serial data transmission devices from sending out data at a time. The connecting apparatus can be connected with personal computers, serial printers, plotters or modems in series for data transmission to and from one another, and therefore jumper cables between either two data transmission devices are eliminated. Furthermore two connecting apparatus may be interconnected through RJ45 telephone bus cables, therefore it is easy to install and to expand data transmission devices.

Abstract: Jitter provided from a phase locked loop circuit is extracted by pulse extracting circuits. Determination is made by a counter whether a pulse signal representing the jitter reaches a predetermined number within a predetermined time period. An evaluation signal representing the level of the jitter is provided from a thermometer decoder according to the determination result.

Abstract: A programmable apparatus is disclosed for generating a frequency modulated signal all a selected center frequency in accordance with digital data of at least first and second data levels. The modulating apparatus comprises a modulator having an input and an output and is responsive to an input modulation signal applied to its input for generating at its output the frequency modulated signal at a center frequency dependent on a quiescent voltage appearing at its input. A circuit is provided for sampling and storing a value of the quiescent voltage, An addressable memory stores a plurality of offsets. A programmable adding circuit adds a downloaded offset voltage to the stored value of the quiescent voltage to output a high modulation voltage. A programmable subtracting circuit subtracts a downloaded offset voltage from the stored value of the quiescent voltage to provide a low modulation voltage.

Abstract: A system and method for decreasing the amount of bandwidth required to transmit a high bandwidth signal over electrically conducting transmission lines, wherein the transmission lines are arranged in a symmetrical configuration so that their propagation characteristics permit frequency independent modes of propagation of a plurality of signals to be transmitted thereon. This permits decomposing a high bandwidth signal into lower bandwidth signals, and then encoding these lower bandwidth signals in association with the frequency independent modes of propagation, driving the individual electrically conducting transmission lines with these encoded signals, and then decoding and recombining the signals at the receiving end to recapture the high bandwidth signal.

Abstract: A method and apparatus for attenuating jitter in digital signals. A recovered clock is derived from the digital signal and the digital signal is stored in a buffer. The derived clock is input to an input counter which counts a predetermined number of degrees out of phase with an output counter. When the input counter is at a maximum counter value, the output counter value is latched to the address inputs of a ROM look-up table, which outputs a coefficient to a numerically controlled oscillator (NCO). The NCO includes a low frequency portion that adds the coefficient successively to itself and outputs a carry out (CO) signal. A high frequency portion of the NCO receives a high frequency clock and preferably divides down the high frequency clock to a clock frequency which is centered at the desired output frequency. The high frequency portion preferably includes an edge detect circuit that receives the CO signal and adjusts the frequency of the output clock to produce a compensation clock.