Abstract: An equalization method for digitally encoded signals transmitted in a plurality of non-contiguous time slots has a digitally encoded synchronization signal commencing in each time slot followed by a digitally encoded data signal having a digitally encoded marker signal at a predetermined time period. The synchronization signal of the assigned time slot ("first synchronization signal") and the digitally encoded data signal of the assigned time slot including the marker signal, and the digitally encoded synchronization signal of the immediately succeeding non-assigned time slot ("second synchronization signal") are all stored. The location of the minimum energy point of the stored digitally encoded signals is determined. Equalization is performed starting from the first synchronization signal to the minimum energy point. Then, the equalization commences from the second synchronization signal backwards until the minimum energy point is reached.

Abstract: A method for selecting the best survivor from a plurality of surviving possible distal data symbols creates a channel estimate for each of the survivors independent of the others. The likelihood of each survivor is then evaluated, whereupon the most likely survivor is selected. The likelihood of each survivor is computed based only on its own channel estimate. A data sequence estimation system includes a memory for storing a plurality of "surviving" sequences. For each stored survivor, the system includes a channel estimator and a metrics computer, which calculates a measure of the likelihood of the survivor as a function of the survivor itself, the observed input, and the parameters of the associated channel estimator. The system also includes a processor that accumulates the metric and selects a best survivor as a function of a computed maximum likelihood.

Abstract: A receiver (30) in a digital communication system determines the phase error magnitude (60) and the magnitude error (54) for each received channel symbol and selects Reed-Solomon symbol erasures from the magnitude error and phase error magnitude values as a function of mobile unit speed (52) which is determined from demodulator data. The selected symbol erasures are implemented (78) in a Reed-Solomon decoder resulting in improved decoding performance.

Abstract: The present invention discloses a frequency stabilizing circuit used for a modulator that modulates an image signal including a synchronous signal into a pulse modulation signal. The frequency stabilizing circuit comprises a detecting device for detecting the synchronous signal included in the image signal that has not been modulated to output a pulse based on the detection, a pulse generating device for outputting a pulse by extracting a modulated signal outputted from the pulse modulator corresponding to the synchronous signal, and a feedback controlling device for increasing and/or decreasing a level of the image signal to be inputted to the pulse modulator in accordance with the difference between the pulse width of the pulse signal outputted from the detecting device and that of the pulse signal outputted from the pulse generating device.

Abstract: The device (100) and method (700) of the present invention provides for detecting and correcting loss of frame synchronization in a communication system with multi-level trellis coding without additional allocation of channel capacity for such detection and correction.

Abstract: A surrounding circuit for the local area network transceiver comprises isolation transformer, electric resistance, Diodes, transmitting circuit, transistor, electric capacitor, and input circuit; in order to slow down the rising time and falling time of the signal, the circuit can effectively improve the output signal waveform at the secondary coil of the isolation transforming and make it similar to sine wave which decreases the possibility of high frequency radiation. The circuit also provides a receiving surrounding circuit connected to the output of the transmitting surrounding apparatus which can eliminate the Common Mode Noise, has the effect of isolation, and at the same time allows the low-frequency collision signal to enter the transceiving circuit and maintains enough high input impedance.

Abstract: The Multiplierless Quadrature Mirror Filter concept is used in the design of analysis and synthesis filter banks to be used for the sub-band coding of various types of signals. The individual filters in the analysis and synthesis filter banks are designed to be near linear in phase, non-symmetrical in time, and to have equal bandwidth frequency responses. These multiplierless filters are relatively easy to implement in hardware and allow for the sub-band coding of signals with minimal computational complexity so as to result perfect signal reconstruction. Furthermore, these filters are particularly well suited for configuration in hierarchical sub-band structures.

Abstract: In a noise shaper comprising integrators of three or more stages, a quantizer and a feedback circuit, there are provided a circuit for subtracting from an output of each of the integrators a result obtained by delaying the output of the same integrator by one sample and multiplying it by a constant number, so as to output the result of the subtraction to an integrator at the subsequent stage, and a circuit for feeding back a result obtained by delaying an output of the quantizer by one sample and multiplying it by any constant number value, to an input of each of the integrators.

Abstract: A method and apparatus for normalizing the I and Q components of a complex signal is provided which includes an iterative determination of the multiplier constant required for normalization. The I and Q components are squared and added together to create a digital word A constrained between certain limits. An iterative approach is implemented to arrive at a multiplier constant K which is equal to ##EQU1## without resorting to the use of multipliers. The constant K is then used to normalize the I and Q components.

Abstract: The present invention relates to a QAM signal demodulation system able to recover phase and frequency of the carrier and convert the signal to baseband, and to perform these functions when frequency errors are remarkable with respect to the symbol frequency (low capacity links); to reconstruct the synchronism of symbol in order to correctly sampling the analog signal to be processed; to complete the shaping of the signal through a digital filter and to equalize the baseband converted signal (in order to compensate the selective fading effects due to propagation and the linear distortions due to imperfections in the realization of the apparatus). Therefore the system comprises several subsystems devoted to performing the various functions and, in particular, at least a carrier frequency and phase recovery subsystem, a subsystem for reconstructing the synchronism frequency capable of driving the signal sampling circuit, and a subsystem of filters.

Abstract: A digital phase locked loop which incorporates a phase comparator which produces a phase deviation signal having a sinusoidal phase comparison characteristic rather than a sawtooth phase comparison characteristic in order to avoid aliases.

Abstract: A serial data transmission system employing at least three transmission lines for transmitting the serial data. Each of the transmission lines can be designated as a data line 1 or as a data line 2. An encoder dynamically designates, for each binary data bit transmission period, one transmission line as data line 1 and one transmission line as data line 2 such that the transitions representing two data bits being transmitted in two successive transmission periods not occur on any one of the transmission lines. In each binary data bit transmission period, the encoder will cause a transition to occur on either data line 1 or data line 2 as a function of the value of the data bit to be transmitted during that transmission period.

Abstract: The decoding process of the present invention receives encoded data over a channel, decodes the data, and estimates the number of errors induced by the channel. The decoded date is stored in memory. If no errors were detected, the data stored in memory is used as the decoded signal. The process of the present invention requires reduced processing time by the processor thereby reducing the power requirements of the processor.

Abstract: In a receiver for digitally modulated signals in mobile communication systems, the reception signal can be represented as a complex vector. The signal undergoes homodyne or heterodyne incoherent conversion into the baseband by means of a mixing stage with mixers M. This involves splitting into the real component and the imaginary component. The signal components are filtered by low-pass filters (TP) and digitized with analog-digital converters (AD). The sampled values are converted into the magnitude and angle of the vector. The magnitude value (B) controls the gain of the preamplifier (VV) and of the low-pass filters (TP), the reception data (D) are recovered from the difference between two successive angle values (W).

Abstract: In a system in which a non-random, noise-free signal is disturbed by random noise, one first determines a way to measure the difference between two signals, and one also selects a measure of complexity for signals. Based on a series of discrete values of the noisy signal, a compression processor generates a series of compressed signals representing the noisy signal, each within a corresponding error or loss tolerance of the discrete values of the noisy signal. An optimization processor applies the various loss tolerance values to the compression processor and then evaluates the relative complexity of the corresponding compressed signals. The optimization processor then determines an optimal knee point loss tolerance, below which the complexity of the compressed signals rises rapidly. For continued filtering of the noisy signal, the compression processor compresses the noisy signal using the optimal knee point loss tolerance.

Abstract: A method of detecting whether a valid DS1 signal is being received by a receiver. If the receiver does not have a valid signal (loss of signal), then the receiver reads consecutive fixed sized N bit blocks of the received digital signal. Each of the blocks or windows is checked for minimum 1s density. Received consecutive 0s are counted and checked against a maximum. If two sequential blocks of bits satisfy the 1s and consecutive 0s tests, then the received signal is judged valid and an acquisition of signal flag is asserted.

Abstract: In an interference canceller, a feedforward filter receives an input signal to produce an equalized feedforward output signal in which CW interference is cancelled and a feedback filter receives the output of a decision circuit to produce an equalized feedback output signal. The equalized feedforward and feedback output signals are combined together to cancel intersymbol interference before being applied to the decision circuit. First tap-gain control circuits derive first tap-gain signals from a decision error and signals at the first delay-line taps and respectively apply these signals to the first tap-gain multipliers. Second tap-gain control circuits derive second tap-gain signals from the decision error and signals at the second delay-line taps and respectively apply these signals to the second tap-gain multipliers. A complex correlation is detected between signals at opposite ends of the first tapped delay line and compared with a threshold.

Abstract: A digital RF receiving system is provided for processing relatively weak analog signals transmitted in a noisy environment. The system includes a receiver for filtering and mixing the incoming signal. Automatic gain control components are provided for digitally attenuating the signal before processing by the receiver so that useful information contained in the signal will not be lost due to saturation of the amplifier within the receiver. The automatic gain control components include a high speed A/D converter, digital processor, and digital attenuator driven by the digital process in response to the signal received from the high speed A/D converter. A second relatively high speed A/D converter samples and digitizes the output signal from the receiver at a relatively high rate. A microprocessor is included for digitally filtering and processing the digitized signal from the A/D converter into useful digital information.

Abstract: An improved digital communications system is disclosed in which synchronization information is transmitted with the data. A start pulse, having a duration different than the other pulses in the transmitted digital data signal is used to mark the beginning of the frame of digital data. Preferably, a midpoint pulse is also transmitted with the start pulse to mark the midpoint of the frame to facilitate the generation of a local clock signal. Bit positions within the transmitted signal are sampled by sampling pulses which are generated by digital timers having time intervals keyed to the start and midpoint pulses.

Abstract: The high requirements of digital mobile radiotelephone communication under the GSM Standard with respect to synchronization of a mobile radiotelephone to a fixed radiotelephone station is performed by frequently (four times per so-called baseband frequency cycle) sampling contemporary in-phase and quadrature phase components of received GMSK digital signals and utilization of time slots respectively containing a frequency correction burst, a normal burst and an extended synchronization burst, respectively for initial synchronization, normal maintenance of synchronization during communication and a background procedure during normal operation. The decoding of the GMSK signal provides one-bit of information from each pair of in-phase and quadrature components sampled. The sampling of in-phase and quadrature components greatly simplifies the synchronizing procedure.