Abstract: A method for forming an HSG (hemispherical grain) layer on a storage electrode of a capacitor formed on a substrate is provided. The method includes a step of introducing a source gas into a reacting chamber to deposit a small amount of HSG nuclei on a conductive layer pattern of a capacitor electrode during a step of stabilizing the substrate temperature. After the substrate temperature is stabilized, a larger amount of source gas is introduced into the chamber to form additional HSG nuclei. Thereafter, a step of annealing is performed to form the HSG layer.

Abstract: A method of forming a transistor in a peripheral circuit of a random access memory device wherein a transistor gate, capacitor electrode or other component in the memory cell array is formed simultaneously with the formation of a transistor gate in the periphery.

Abstract: A floating gate transistor has a reduced barrier energy at an interface between a gallium nitride (GaN) or gallium aluminum nitride (GaAlN) floating gate an adjacent gate insulator, allowing faster charge transfer across the gate insulator at lower voltages. Data is stored as charge on the floating gate. The data charge retention time on the floating gate is reduced. The data stored on the floating gate is dynamically refreshed. The floating gate transistor provides a dense and planar dynamic electrically alterable and programmable read only memory (DEAPROM) cell adapted for uses such as for a dynamic random access memory (DRAM) or a dynamically refreshed flash EEPROM memory. The floating gate transistor provides a high gain memory cell and low voltage operation.

Abstract: An infrared optical field effect transistor has been developed using a thin film of Lead Titanate (PbTiO3) deposited on a n/p+ Si substrate by RF magnetron sputtering. This transistor possesses excellent pyroelectric properties and can, therefore, be operated even at room temperature. The infrared optical field effect transistor has the following features associated with rapid bulk channel structure and higher mobility: 1. Can be operated at room temperature, unlike quantum type IR sensors which can only operate at very low temperature (−100° C.˜−200° C.), which results in higher costs. 2. High speed response with only 2.3 &mgr;s of rise time. This is much faster than other types of thermal infrared optical field effect transistors. 3. Easy to fabricate an integrated sensor device.

Abstract: Highly refractory titanium silicide structure comprises a titanium silicide film formed on a silicon crystal surface and a thermal oxide film formed on this titanium silicide film. A manufacturing method of the highly refractory titanium silicide is as follows. Initially, titanium is deposited on surfaces including a silicon crystal surface to form a titanium film (12) of a predetermined thickness. This titanium film (12) is then heat-treated in vacuum or in a certain atmosphere which does not cause any oxidation, to form a titanium silicide film (13). Subsequently, further heat treatment at temperatures between 600° C. and 1,000° C. in oxygen atmosphere is done for a predetermined time to oxidize the surface of the titanium silicide film (13). This oxidization of the surface of the titanium silicide film (13) restrains agglomeration in the titanium silicide which might occur in the subsequent annealing, so that the resistance value increase can be prevented.

Abstract: A radiation detection structural principle for improved detection wherein absorbtion members of high density and bandgap semiconductor material and meeting all efficiency limiting requirements are provided with a sweeping field applied across each member. The absorbtion members are assembled in stack structures for particular energy resolution benefits. The detector principle is extendable to long absorbtion paths and to energy resolution in specific areas.

Abstract: The inventive method provides improved semiconductor devices, such as MOSFET's with raised source/drain extensions on a substrate with isolation trenches etched into the surface of the substrate. The inventive method provides thin first dielectric spacers on the side of a gate and gate oxide and extend from the top of the gate to the surface of the substrate. Raised source/drain extensions are placed on the surface of a substrate, which extend from the first dielectric spacers to the isolation trenches. Thicker second dielectric spacers are placed adjacent to the first dielectric spacers and extend from the top of the first dielectric spacers to the raised source/drain extensions. Raised source/drain regions are placed on the raised source/drain extensions, and extend from the isolation trenches to the second dielectric spacers. The inventive semiconductor devices provide for very shallow source drain extensions which results in a reduced short channel effect.

Abstract: A high-temperature (10 K) superconductive integrated circuit has a ground plane (2), an interlevel dielectric (6), and a low value resistor (18) to provide conductive paths to reduce parasitic circuit inductances, thereby increasing the speed and performance of the integrated circuit. The circuit also includes a high value resistor (20) connected between interconnect wires (34) to produce a desired resistance with a short distance between the interconnect wires (34), thereby significantly reducing the circuit area.

Abstract: A first insulator film and a first polysilicon film are formed on first and second element regions of a semiconductor substrate. The first insulator film and first polysilicon film are removed from the second element region. A second insulator film is formed on the second element region from which the first insulator film and first polysilicon film are removed, and a second polysilicon film is formed on the second insulator film. The first polysilicon film is processed, forming a first gate electrode at the first element region. The second polysilicon film is processed, forming a second gate electrode at the second element region. A silicon nitride film is removed from an element-isolation region. A metal film is formed on the region from which the silicon nitride film has been removed, and connects the first and second gate electrodes.

Abstract: In a silicon carbide static induction transistor, at a surface part of a semiconductor substrate, a p-type gate region is formed partially overlapping a n-type source region, whereby the high accuracy in alignment between the gate region and the source region is not required, and the gate withstand voltage can be highly increased since the substrate is made of silicon carbide, which improves the yield of static induction transistors.

Abstract: A system and method for marking a chip-scale package is disclosed. In one aspect, the chip-scale package includes a semiconductor die. The semiconductor die has an exposed portion substantially surrounded by the first coating. In this aspect, the method and system include applying a second coating to a first portion of the first coating and marking the second coating. The first coating is not completely penetrated by the marking. In a second aspect, the method and system include providing a chip-scale package. In this aspect, the method and system comprise providing a substrate, providing a semiconductor die coupled to a substrate, and providing a first coating. The semiconductor die has an exposed portion. The exposed portion is substantially surrounded by the first coating. In this aspect, the method and system further include providing a second coating substantially covering a first portion of the first coating. The second coating has a plurality of markings therein.

Abstract: In a static induction semiconductor device, particular a high power static induction semiconductor device, recessed portions 12 are formed in one surface of a silicon substrate 11 of one conductivity type, gate regions 13 of the other conductivity type are formed at bottoms of the recessed portions, recessed portions 14 are formed at portions surrounded by adjacent gate regions, cathode short-circuit regions 15 of the other conductivity type are formed as an island at bottoms of the recessed portions to be extended to the surface of the silicon substrate. Cathode regions 17 extending up to the surface of the silicon substrate in succession to channel regions 16 surrounded by the cathode regions 13 and cathode short-circuit regions 15, are formed. A cathode electrode substrate 21 is formed to be contacted with the cathode short-circuit regions 15 and cathode regions 17.

Abstract: A field effect transistor is formed across a one or more trenches (26) or bars (120), thereby increasing the effective width of the channel region and the current-carrying capacity of the device.

Abstract: A method for forming a field effect transistor (FET) is disclosed which includes forming an isolation region in a substrate of semiconductor material, anisotropically etching the substrate such that a sidewall spacer region of semiconductor material remains on a sidewall of the isolation region as a device region of the FET. The isolation region may then be recessed such that, after gate conductor deposition, the central channel region of the device region is enclosed by the gate conductor. A dopant concentration in at least one of the central portion of the device region or regions flanking the central portion are then altered to form source-drain regions having a first dopant type and a channel region having a second dopant type opposite the first dopant type.

Abstract: The power semiconductor component has a semiconductor body which is electrically supplied through a contact clip. A solder ball connects the semiconductor body to the contact clip. The contact clip has a meandering electrical supply to a solder land, into which the solder ball is inserted.

Abstract: A single crystal silicon substrate (1) is bonded through an SiO2 film (9) to a single crystal silicon substrate (8), and the single crystal silicon substrate (1) is made into a thin film. A cantilever (13) is formed on the single crystal silicon substrate (1), and the thickness of the cantilever (13) in a direction parallel to the surface of the single crystal silicon substrate (1) is made smaller, than the thickness of the cantilever in the direction of the depth of the single crystal silicon substrate (1), and movable in a direction parallel to the substrate surface. In addition, the surface of the cantilever (13) and the part of the single crystal silicon substrate (1), opposing the cantilever (13), are, respectively, coated with an SiO2 film (5), so that an electrode short circuit is prevented in a capacity-type sensor. In addition, a signal-processing circuit (10) is formed on the single crystal silicon substrate (1), so that signal processing is performed as the cantilever (13) moves.

Abstract: A method for treating a film of material, which can be defined on a substrate, e.g., silicon. The method includes providing a substrate comprising a cleaved surface, which is characterized by a predetermined surface roughness value. The substrate also has a distribution of hydrogen bearing particles defined from the cleaved surface to a region underlying said cleaved surface. The method also includes increasing a temperature of the cleaved surface to greater than about 1,000 Degrees Celsius while maintaining the cleaved surface in a etchant bearing environment to reduce the predetermined surface roughness value by about fifty percent and greater. Preferably, the value can be reduced by about eighty or ninety percent and greater, depending upon the embodiment.

Abstract: A shared contact is provided on the side of a drain active region of each of two load transistors. Thus, a stabilized low voltage operation is ensured in a full CMOS type SRAM memory cell having the shared contact.

Abstract: There is provided a method of fabricating a semiconductor device, including the steps of, in sequence, (a) partially forming a buried layer in a semiconductor substrate and also forming an epitaxial layer on the buried layer, (b) forming a collector region in the epitaxial layer by selectively introducing impurities into the epitaxial layer so that the collector region reaches the buried layer, (c) forming an insulating film on the epitaxial layer, (d) forming a polysilicon film on the insulating film, (e) patterning the polysilicon film to form a base electrode, (f) forming an interlayer insulating film over the base electrode and the insulating film, (g) patterning both the interlayer insulating film and the base electrode to form a base opening at a region at which a base region is to be formed and a collector opening above the collector region, (h) side-etching portions of the insulating film located below the base electrode to form undercut hollow portions in the insulating film, (i) filling the undercut

Abstract: A system and method for deprocessing a semiconductor die is disclosed. The semiconductor dies has an active area and at least one feature in the active area. The method and system include tuning an ablation laser. The method and system further include ablating a first portion of the semiconductor die using a tuned ablation laser to mark a location of the feature. The first portion is distinct from the active area and has a center. The center of the first portion is substantially above the feature. The method and system also include deprocessing a second portion of the semiconductor die using the first portion as a guide.