Abstract: A field effect transistor (FET) with a V-shaped trench gate in a semiconductor substrate having gate oxide on the walls of the trench and a gate electrode material within the trench walls, and source/drain impurities in the semiconductor substrate and abutting the gate oxide. The resultant FET structure comprises a non-self align V-shaped gate with an effective channel length (L.sub.eff) of less than about one-half of the surface width of the gate. Because of the V-shaped structure of the gate, the effective length of the channel only extends from the edge of the source to the tip of the V-shaped gate. Due to this characteristic, the width of the gate at the surface of the semiconductor substrate can be two or more time the distance of the desired channel length thereby permitting conventional lithography to be used to fabricate gate lengths much shorter than the lithography limit. Preferably, the bottom or tip of the V shaped gate is rounded and concave.

Abstract: Metallic osmium on SiC (either .beta. or .alpha.) forms a contact that remains firmly attached to the SiC surface and forms an effective barrier against diffusion from the conductive metal. On n-type SiC, Os forms an abrupt Schottky rectifying junction having essentially unchanged operating characteristics to at least 1050.degree. C. and Schottky diodes that remain operable to 1175.degree. C. and a barrier height over 1.5 ev. On p-type SiC, Os forms an ohmic contact with specific contact resistance of <10.sup.-4 ohm-cm.sup.2. Ohmic and rectifying contacts to a TiC layer on a SiC substrate are formed by depositing a WC layer over the TiC layer, followed by a metallic W layer. Such contacts are stable to at least 1150.degree. C. Electrodes connect to the contacts either directly or via a protective bonding layer such as Pt or PtAu alloy.

Abstract: Disclosed are methods of making inductors and capacitors, comprising filling a via in a dielectric disposed between two metal layers with a metal plug. The plug comprises tungsten, aluminum or copper and extends the length of the metal layers. The plug connects the two metal layers to form the inductor. Two plugs can be formed so as to connect the two metal layers so as to form a parallel plate capacitor.

Abstract: A full CMOS SRAM cell having the capability of having a reduced aspect ratio is described. The SRAM cell includes first and second transfer transistors of n-channel types, first and second driving transistors of the n-channel types and first and second load transistors of p-channel types. Each of the transistors has source and drain regions on opposite sides of a channel region formed in a semiconductor substrate and a gate over the channel region. The cell includes a first common region defined by the drain regions of the first transfer transistor and the first driving transistor connected in series therethrough. A second common region is defined by the drain regions of the second transfer transistor and the second driving transistor connected in series therethrough. The drain region of the first load transistor is disposed adjacent to the first common region between the first and second common regions.

Abstract: A process for the preparation of hermetically sealed electronically active microstructures involves the preparation of a plurality of microstructures and associated conductive paths and lead bond areas on a single wafer such that areas surrounding the microstructures are maintained in a planar condition. A second wafer having a plurality of microstructure-receiving cavities is placed atop the first wafer and fusion or anodically bonded. The microstructures are preferably connected to lead bond pads which lie outside the surround, the second wafer also having bond pad accessing through-holes to facilitate bonding electrical leads to the devices after sawing from the wafer. The lead-connected devices may be further encapsulated by injection molding, potting, or other conventional encapsulative packaging techniques.

Abstract: A PMOS or CMOS device includes an active region with a shallow heavy atom p-type implant. The PMOS device has a substrate, at least one gate electrode disposed on the substrate, and first and second doped active regions disposed adjacent to the gate electrode. The first active region has a higher concentration of a p-type heavy atom dopant material than the second active region. In one method of forming the PMOS device, spacers are formed on sidewalls of the gate electrode. A first p-type dopant material is selectively implanted into active regions adjacent to the gate electrode using the spacers as a mask. Then a portion of one of the spacers is removed to form a thinner spacer and a second p-type dopant material is selectively implanted into a first one of the active regions using the thinner spacer as a mask. The second p-type dopant material is a heavy atom species.

Abstract: An interlevel interconnect is formed in a window opened through an isolation layer and through an etch barrier to expose an electrode surface and an adjacent isolation barrier. The interlevel interconnect may be disposed on substantially all of a portion of the underlying electrode such as an insulated gate field effect transistor (IGFET) source/drain region surface. The etch barrier provides controlled etching to allow for overlap of the interlevel interconnect onto the isolation barrier without increased parasitic capacitance relative to conventional contact misalignments. Furthermore, allaying concerns of overlapping allows for increased utilization of source/drain region surface area by the interlevel interconnect. Furthermore, the etch barrier allows the interlevel interconnect to strap electrodes of a plurality of circuit devices while exhibiting nominal if any substrate to interlevel interconnect leakage currents.

Abstract: The present invention discloses a pad for establishing instant electrical connection (PIEC) for in-line ion measurement device. The PIEC pad employs low-melting-point conductive materials, such as gallium or indium, as the attaching contact materials. The melting points of these materials can be below 160.degree. C. The vapor pressures of these materials are generally lower than 10.sup.-5 mm Hg in the temperature range between 100-300.degree. C. A PIEC pad is formed on a heavily doped semiconductor substrate covered with a metal layer. A layer of low-melting-point low-vapor-pressure material, e.g., gallium or indium, is then formed on the bottom of the heavily doped substrate. By heating a measuring device, the temperature is raised and the bottom low-melting attaching layer is melted and a good electric contact is established between the PIEC pad and the device for measurement A bonding wire is also formed on top of the metal layer.

Abstract: A method for manufacturing a gate oxide film in a semiconductor device includes: preparing a semiconductor substrate having a first and a second active region; implanting germanium ions into the first active region; and forming a first and a second gate oxide films on the first and the second active regions, respectively, wherein the first gate oxide film is thicker than the second gate oxide film.

Abstract: A power transistor device, for example a MOSFET or an IGBT, comprises a semiconductor body (10) which accommodates an array (11) of parallel device cells (1a) in which heat is generated in operation of the device. A hot-location temperature sensor (Mh) is located inside the array (11), and a cool-location temperature sensor (Mc) is located outside the array (11). These sensors each comprises at least one sensor cell (1b; 1c) which is of the same transistor type as the device cells (1a). The sensor cells (1b; 1c) have a cellular region structure (12,13,14,15) similar to that of the device cells (1a), but each sensor (Mh; Mc) has a respective output electrode (31; 32) separate from electrodes (22,23,25) of the device cells (1a).

Abstract: A method of making an integrated circuit package for EPROM, CCD, and other optical integrated circuit devices is disclosed. First, a substrate base having metallized vias extending there through is provided. Second, an integrated circuit die is affixed to a first surface of the substrate, and is electrically connected to the metallized vias. Third, a bead of a viscous adhesive material is applied onto the substrate around the device. The bead covers the side surfaces of the device, the periphery of the upper first surface of the device, and the bond wires. The bead and the upper first surface of the die form a cavity above the die. Fourth, a layer of a transparent encapsulating material is deposited onto the die, within the cavity formed by the bead. Fifth, the encapsulating material is hardened, and subsequently forms an exterior surface of the package. The transparent encapsulating material allows light to illuminate the light sensitive circuitry of the device.

Abstract: A microwave integrated circuit package is disclosed. The package consists of a package substrate, having conductive vias, at least one ground plane, and conductive transmission lines; a semiconductor die electrically and mechanically connected to the top surface of the package substrate; a continuous outer wall attached to the top surface of the package substrate and at least one interior wall at a distance from a second wall, which may be the outer wall; a lid; at least one of the transmission lines passing under the interior wall and the second wall carrying a signal of frequency F; and an impedance transformer on the transmission line between the interior wall and the second wall. In operation, the interior wall, the distance between the interior wall and the second wall and the impedance transformer cancel the discontinuity caused by the second wall whereby the reflection of the signal caused by the transmission line passing under the walls is greatly diminished.

Abstract: A method for fabricating a photodiode is described in which a pad oxide layer and a silicon nitride layer are sequentially formed on a provided substrate. The silicon nitride layer, and the pad oxide layer and the substrate are sequentially patterned to form an opening in the substrate. A spacer is formed on the sidewall of the opening. With the spacer and the silicon nitride layer serving as a mask, the substrate is etched forming a trench in the substrate. An oxide plug is then formed filling the trench and the opening using the conventional shallow trench fabrication method. A P-well region and an N-well region are formed respectively on two sides of the trench.

Abstract: Complementary vertical bipolar and DMOS devices are formed in a single substrate with fully isolated wells and retrograde well doping. The retrograde well doping results from a process in which the complementary wells are formed in a silicon substrate and heavily doped collector regions formed at the surface. The wafer is then inverted and the backside of the wafer ground away exposing the retrograde doped wells. With appropriate well doping complementary IGBT devices can be integrated with bipolar and/or DMOS devices in the same substrate. Trench technology is used for isolation.

Abstract: A self-protected output driver for an integrated circuit utilizing cascode configured MOSFET transistors is formed in a single active region, allowing a smaller layout area without sacrificing performance. Furthermore, the driver is laid out according to a standard cell layout and is adaptable for a variety of output driving specifications according to the need of a particular implementation. A doped region having a first conductivity type is formed in the substrate. A plurality of sets of cascode connected transistors having channels in the doped region is included.

Abstract: A ferroelectric non-volatile memory in which each memory cell consists of a metal-ferroelectric-metal ("MFM") capacitor and a FET on a semiconductor substrate. The MFM and the FET are separated by an interlayer dielectric layer. A local interconnect connects the gate electrode of the FET to the bottom electrode of the MFM capacitor. Preferably, the MFM is located directly above the gate electrode, and the local interconnect is a conductive plug in a filled via. Preferably, the ferroelectric thin film of the MFM comprises a layered superlattice material. Preferably, a dielectric metal oxide insulator layer is located between the gate electrode and the semiconductor substrate.

Abstract: A FET device comprising a semiconductor substrate; diffusion regions in the substrate separated by a channel region; a gate overlapping the channel region and a portion of the diffusion regions and separated from the substrate by a gate dielectric; and a sidewall dielectric on a sidewall of the gate; and a sidewall spacer conductor on the sidewall dielectric contacting one of the diffusion regions but not both of the diffusion regions of one device is provided along with a method for its fabrication. The conductive spacer connects diffusions of adjacent devices that share a common gate electrode.

Abstract: The present invention relates to a method for arrangement of a buried capacitor on a substrate or the like, and a buried capacitor arranged according to the method. In order to diminish the resistive losses in a capacitor and to make it more efficient, in semi-conductor circuits, instead of the polycrystalline layer, one or more bodies of metal such as aluminum or tungsten may be used. This has been made possible using a new technique in which a trench filling of conducting material is etched away without removal through etching of the insulating layer in the trench. After the removal through etching of the trench filling, the trench is filled using the metal as above, whereby the insulating layer between the conducting material and the metal body will separate two conducting surfaces, thereby forming the buried capacitor.

Abstract: A method of fabricating a semiconductor device an object of which is to form a semiconductor device having a DMOS with high withstanding pressure and high driving capacity and a highly precise polycrystalline silicon resistor. In the method of fabricating a semiconductor device, by patterning a second polycrystalline silicon resistor using anisotropic etching, the size precision is improved. Further, during the patterning, side spacers are formed on gate electrode side walls formed of first polycrystalline silicon at the same time. The body of the DMOS is doped with the gate electrode and the spacers being the mask. A source region is doped with the gate electrode being the mask after the spacers are removed.