Patents Examined by Douglas A. Wille
  • Patent number: 7118932
    Abstract: A method of manufacturing a waveguide type optical element wherein Zn is selectively diffused on a light absorption layer using an undoped InP layer. Since an impurity diffusion area is made on the light absorption layer under a ridge part, a depletion layer becomes thin in a thickness direction and an electric field can strongly be applied. Thereby, an extinction ratio characteristic of a device can be improved.
    Type: Grant
    Filed: January 31, 2002
    Date of Patent: October 10, 2006
    Assignee: Oki Electric Industry Co., Ltd.
    Inventor: Koji Nakamura
  • Patent number: 7071542
    Abstract: A lead frame includes at least two layers, each of which includes an electrically conductive bus and a group of leads that extend substantially unidirectionally from a single edge of the lead frame. The lead fingers of each layer may extend in substantially the same direction. The electrically conductive buses of the two or more lead frame layers are at least partially superimposed with respect to one another. An insulator element is disposed between at least portions of the superimposed regions of the buses. One of the buses is connectable to a power supply source (VCC), while the other is connectable to a power supply ground (VSS). Thus, the mutually superimposed regions of the buses form a decoupling capacitor. Lead fingers of one of the layers may be arranged in groups which flank the remainder of the lead fingers so that they are not interleaved therewith.
    Type: Grant
    Filed: October 11, 2002
    Date of Patent: July 4, 2006
    Assignee: Micron Technology, Inc.
    Inventors: David J. Corisis, Chris G. Martin
  • Patent number: 7033913
    Abstract: A semiconductor device comprises a base substrate, an insulating film formed on the substrate, an undoped first and lattice-relaxed semiconductor layer formed on the insulating film, a second semiconductor layer having a tensile strain and formed on the first semiconductor layer, and a MISFET formed on the second semiconductor layer. Since the MISFET is formed in a strained Si layer, electrons are prevented from scattering in a channel region, improving the electron mobility. Furthermore, since the MISFET is formed in a thin SOI layer having a thickness of 100 nm or less, it is possible to reduce a parasitic capacitance in addition to the improvement of the electron mobility. As a result, the MISFET excellent in drivability can be obtained.
    Type: Grant
    Filed: December 17, 2003
    Date of Patent: April 25, 2006
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Koji Usuda, Shinichi Takagi
  • Patent number: 7024121
    Abstract: Proposed is an optical clock distribution system in the WDM network, which particularly relates to a system to control clock synchronization between optical transmission devices constituting an optical communication network. The optical clock distribution system includes an optical clock generator converting a clock signal of PRC (Primary Reference Clock) level into an optical clock signal having a wavelength ?0; a wavelength multiplexer wavelength-multiplexing the optical clock signal having wavelength ?0 together with other optical wavelength data; and a wavelength-demultiplexer provided in a unit of the network, wavelength-demultiplexing the optical clock signal having wavelength ?0, wherein the other optical wavelength data are processed in the unit of the network using the wavelength-demultiplexed optical clock signal having wavelength ?0 as a reference clock.
    Type: Grant
    Filed: October 17, 2002
    Date of Patent: April 4, 2006
    Assignee: Fujitsu Limited
    Inventors: Nobuhiro Rikitake, Hirotaka Morita, Koji Takeguchi, Ryuichi Moriya, Hideki Matsui
  • Patent number: 7019341
    Abstract: A silicon-germanium hetero bipolar transistor comprising a silicon collector layer, a boron-doped silicon-germanium base layer, a silicon emitter layer and an emitter contact area. The transistor is fabricated using an epitaxy process on a surface of pure silicon. An electrically inert material is incorporated into the epitaxial layers in order to link the defects in the semiconductor structure and to reduce the outdiffusion of the dopant. Thus, a transistor for high-frequency applications can be fabricated in two ways: to increase the dopant dose of the base region or to reduce the thickness of the base layer. In particular, the concentration profile of germanium in the base layer has a general shape of a triangle or trapezoid.
    Type: Grant
    Filed: August 30, 2002
    Date of Patent: March 28, 2006
    Assignee: IHP GmbH - Innovations for High Performance Microelectronics/Instut fur Innovative Mikroelektronik
    Inventors: Gunther Lippert, Hans-Jörg Osten, Bernd Heinemann
  • Patent number: 7019382
    Abstract: To protect a high-frequency integrated circuit (1) against higher voltages than normal operating voltages on an input/output terminal connected to a bonding pad (2), a semiconductor varistor (3) having low and essentially constant resistance for said normal operating voltages and higher resistance for said higher voltages is integrated between the bonding pad (2) and the input/output terminal together with the integrated circuit (1).
    Type: Grant
    Filed: March 2, 2004
    Date of Patent: March 28, 2006
    Assignee: Infineon Technologies AG
    Inventors: Andrej Litwin, Ola Pettersson
  • Patent number: 7019324
    Abstract: The present invention provides a MOSFET device comprising: a substrate including a plurality of atomic ridges, each of the atomic ridges including a semiconductor layer comprising Si and an dielectric layer comprising a Si compound; a plurality nanogrooves between the atomic ridges; at least one elongated molecule located in at least one of the nanogrooves; a porous gate layer located on top of the plurality of atomic ridges. The present invention also provides a membrane comprising: a substrate; and a plurality of nanowindows in the substrate and a method for forming nanowindows in a substrate.
    Type: Grant
    Filed: October 10, 2002
    Date of Patent: March 28, 2006
    Assignee: Starmega Corporation
    Inventor: Don Kendall
  • Patent number: 7009219
    Abstract: A small, simple current-injection diamond ultraviolet light-emitting device comprising a high-quality diamond grown by chemical vapor deposition (CVD) method (1), a surface conductive layer (2) provided on the surface of the diamond, and electrodes (4, 5) provided on the surface conductive layer. The device is a free-exciton recombination emission diamond ultraviolet light-emitting device comprising a CVD diamond crystal where the free-exciton recombination radiation (235 nm) caused by current injection is dominant.
    Type: Grant
    Filed: June 27, 2000
    Date of Patent: March 7, 2006
    Assignee: Tokyo Gas Co., Ltd.
    Inventors: Takefumi Ishikura, Kenji Horiuchi, Satoshi Yamashita, Aki Kawamura, Kazuo Nakamura, Kenichi Nakamura, Takahiro Ide
  • Patent number: 7009249
    Abstract: A method of manufacturing a semiconductor device is provided. The method includes providing a device isolation region for defining a device region on a mono-crystalline semiconductor layer of an SOI substrate formed with a mono-crystalline semiconductor layer through an embedded insulation payer on a semiconductor substrate of a first conductivity type. An opening is formed penetrating the device isolation region and the embedded insulation layer and reaching the semiconductor substrate. A polysilicon is deposited on the SOI substrate and within the opening and providing a gate electrode and a substrate electrode of the MIS type field-effect transistor by executing the patterning thereon; and implanting impurities into the gate electrode and the substrate electrode.
    Type: Grant
    Filed: April 9, 2003
    Date of Patent: March 7, 2006
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Hideaki Nii
  • Patent number: 7005751
    Abstract: A microelectronic spring contact for making electrical contact between a device and a mating substrate and method of making the same are disclosed. The spring contact has a compliant pad adhered to a substrate of the device and spaced apart from a terminal of the device. The compliant pad has a base adhered to the substrate, and side surfaces extending away from the substrate and tapering to a smaller end area distal from the substrate. A trace extends from the terminal of the device over the compliant pad to its end area. At least a portion of the compliant pad end area is covered by the trace, and a portion of the trace that is over the compliant pad is supported by the compliant pad. A horizontal microelectronic spring contact and method of making the same are also disclosed. The horizontal spring contact has a rigid trace attached at a first end to a terminal of a substrate.
    Type: Grant
    Filed: April 10, 2003
    Date of Patent: February 28, 2006
    Assignee: FormFactor, Inc.
    Inventors: Igor Y. Khandros, Charles A. Miller, Stuart W. Wenzel
  • Patent number: 7001829
    Abstract: In a method of manufacturing a semiconductor device, a laser beam capable of irradiating a large area in one shot is irradiated to an amorphous silicon film into which a catalytic element is intentionally introduced to crystallize the amorphous silicon film, thus obtaining a crystalline silicon film.
    Type: Grant
    Filed: June 8, 1999
    Date of Patent: February 21, 2006
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Shunpei Yamazaki
  • Patent number: 7002234
    Abstract: Capacitors are formed of a conductive loaded resin-based material. The conductive loaded resin-based material comprises micron conductive powder(s), conductive fiber(s), or a combination of conductive powder and conductive fibers in a base resin host. The ratio of the weight of the conductive powder(s), conductive fiber(s), or a combination of conductive powder and conductive fibers to the weight of the base resin host is between about 0.20 and 0.40. The micron conductive powders are formed from non-metals, such as carbon, graphite, that may also be metallic plated, or the like, or from metals such as stainless steel, nickel, copper, silver, that may also be metallic plated, or the like, or from a combination of non-metal, plated, or in combination with, metal powders. The micron conductor fibers preferably are of nickel plated carbon fiber, stainless steel fiber, copper fiber, silver fiber, or the like.
    Type: Grant
    Filed: April 16, 2004
    Date of Patent: February 21, 2006
    Assignee: Integral Technologies, Inc.
    Inventor: Thomas Aisenbrey
  • Patent number: 6995465
    Abstract: An apparatus is constituted with an integrated circuit and a flex tape coupled to the integrated circuit. The flex tape is employed to facilitate ingress/egress of signals to/from the integrated circuit. In one embodiment, the flex tape includes a plurality of signal traces. In another embodiment, the apparatus also includes a silicon interposer coupled to the flex tape and a substrate coupled to the silicon interposer.
    Type: Grant
    Filed: June 4, 2003
    Date of Patent: February 7, 2006
    Assignee: Intel Corporation
    Inventors: Dong Zhong, Yuan-Liang Li, Jiangqi He, Jung Kang
  • Patent number: 6995441
    Abstract: An integrated circuit with a number of optical waveguides that are formed in high aspect ratio holes. The high aspect ratio holes extend through a semiconductor wafer. The optical waveguides include a highly reflective material that is deposited so as to line an inner surface of the high aspect ratio holes which may be filled with air or a material with an index of refraction that is greater than 1. These metal confined waveguides are used to transmit signals between functional circuits on the semiconductor wafer and functional circuits on the back of the wafer or beneath the wafer.
    Type: Grant
    Filed: May 8, 2003
    Date of Patent: February 7, 2006
    Assignee: Micron Technology, Inc.
    Inventors: Joseph E. Geusic, Kie Y. Ahn, Leonard Forbes
  • Patent number: 6977421
    Abstract: The invention includes a DRAM array having a structure therein which includes a first material separated from a second material by an intervening insulative material. The first material is doped to at least 1×1017 atoms/cm3 with n-type and p-type dopant. The invention also includes a semiconductor construction in which a doped material is over a segment of a substrate. The doped material has a first type majority dopant therein, and is electrically connected with an electrical ground. A pair of conductively-doped diffusion regions are adjacent the segment, and spaced from one another by at least a portion of the segment. The conductively-doped diffusion regions have a second type majority dopant therein. The invention also encompasses methods of forming semiconductor constructions.
    Type: Grant
    Filed: February 20, 2003
    Date of Patent: December 20, 2005
    Assignee: Micron Technology, Inc.
    Inventors: Mark McQueen, Luan C. Tran, Chandra Mouli
  • Patent number: 6977397
    Abstract: A light emitting element has a substrate of gallium oxides and a pn-junction formed on the substrate. The substrate is of gallium oxides represented by: (AlXInYGa(1?X?Y))2O3 where 0?x?1, 0?y?1 and 0?x+y?1. The pn-junction has first conductivity type substrate, and GaN system compound semiconductor thin film of second conductivity type opposite to the first conductivity type.
    Type: Grant
    Filed: May 30, 2003
    Date of Patent: December 20, 2005
    Assignee: Koha Co., Ltd.
    Inventors: Noboru Ichinose, Kiyoshi Shimamura, Yukio Kaneko, Encarnacion Antonia Garcia Villora, Kazuo Aoki
  • Patent number: 6975010
    Abstract: A fabrication method for a MEMS structure, the MEMS structure including a fixing portion fixed to the substrate and a floating portion floating above the substrate. A sacrificial layer deposited on the substrate is patterned to have a groove forming a space surrounding the area corresponding to the area in which the fixing portion is to be formed. If the MEMS structure is deposited on the sacrificial layer, a sidewall is formed inside the space and the fixing portion and the floating portion are formed on the sacrificial layer. If the sacrificial layer is removed using an etchant, the sacrificial layer at the bottom of the fixing portion is protected from the etchant by the sidewall and accordingly, the sacrificial layer except the area surrounded by the sidewall is removed. Therefore, only the sacrificial layer under the floating portion is removed.
    Type: Grant
    Filed: December 17, 2002
    Date of Patent: December 13, 2005
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Eun-sung Lee, Moon-chul Lee, Hyun-ok Kim
  • Patent number: 6968110
    Abstract: A conventional CMOS fabrication technique is used to integrate the formation of passive optical devices and active electro-optic devices with standard CMOS electrical devices on a common SOI structure. The electrical devices and optical devices share the same surface SOI layer (a relatively thin, single crystal silicon layer), with various required semiconductor layers then formed over the SOI layer. In some instances, a set of process steps may be used to simultaneously form regions in both electrical and optical devices. Advantageously, the same metallization process is used to provide electrical connections to the electrical devices and the active electro-optic devices.
    Type: Grant
    Filed: April 21, 2004
    Date of Patent: November 22, 2005
    Assignee: SiOptical, Inc.
    Inventors: Vipulkumar Patel, Margaret Ghiron, Prakash Gothoskar, Robert Keith Montgomery, Kalpendu Shastri, Soham Pathak, Katherine A. Yanushefski
  • Patent number: 6967369
    Abstract: Processes are disclosed which facilitate improved high-density memory circuitry, most preferably dynamic random access memory (DRAM) circuitry. In accordance with aspects of the invention, considerably greater numbers of die sites per wafer are achieved for 6-inch, 8-inch and 12-inch wafers for 4 M, 16 M, 64 M and 256 M integration levels. Further, a semiconductor memory device includes i) a plurality of functional and operably addressable memory cells arranged in multiple memory arrays formed on a semiconductor die; and ii) circuitry formed on the semiconductor die permitting data to be written to and read from one or more of the memory cells, at least one of the memory arrays containing at least 100 square microns of continuous die surface area having at least 170 of the functional and operably addressable memory cells.
    Type: Grant
    Filed: February 20, 1996
    Date of Patent: November 22, 2005
    Assignee: Micron Technology, Inc.
    Inventors: Brent Keeth, Pierre C. Fazan
  • Patent number: 6965152
    Abstract: A quantum well can be designed to detect light of a particular wavelength by tailoring the potential depth and width of the well. The design produces two energy states in the well separated by the desired photon energy. The GaAs/AlxGa1-xAs material system allows the quantum well shape to be varied over a range wide enough to enable light detection at wavelengths longer than approximately 6 ?m. Hence, large bandgap materials such as GaAs/AlxGa1-xAs material has made fabrication of a large focal plane arrays tuned to detect light at wavelengths from 6 to 25 ?m possible.
    Type: Grant
    Filed: November 23, 1998
    Date of Patent: November 15, 2005
    Assignee: California Institute of Technology
    Inventors: Sumith V. Bandara, Sarath D Gunapala