Abstract: A variable capacitor includes a first component made of conductive material in the form of an at least partially hollow rod, comprising a hole or perforation extending axially into the body of the first component to form a tube portion, and a second component also made of conductive material in the form of a rod able to be fitted to a variable depth into the axial hole, the engagement depth of the second component in the first component determining the degree of capacitive coupling between them and therefore the value of the resulting capacitor. The capacitor tube portion is provided on its internal face, preferably substantially over the whole depth of the axial hole, with a layer of dielectric material, the latter extending in a continuous manner over the edge defining the access aperture of the hole and onto an adjacent part of the external face of the tube portion.

Abstract: A new process flow is provided for the creation of a fuse contact and a bond pad. The invention starts with a semiconductor substrate over the surface of which is provided top level metal and fuse metal in the surface of a layer of insulation deposited over the surface of the substrate. A first etch stop layer is deposited over the surface of the layer of insulation over which a first passivation layer is deposited, an opening is created through these layers exposing the top level metal. A metal plug is created overlying the exposed surface of the top level metal. A stack of a patterned and etched hard mask layers, having been deposited at part of the creation of the metal plug and overlying a layer of metal plug material, remains in place over the surface of the created metal plug.

Abstract: The invention proposes a process for producing electrical contact connections for at least one component which is integrated in a substrate material, the substrate material having a first surface region, and at least one terminal contact being arranged at least partially in the first surface region for each component, which is distinguished in particular by application of a covering to the first surface region and production of at least one contact passage which, in the substrate material, runs transversely with respect to the first surface region, in which process, in order to form at least one contact location in a second surface region which is to be provided, at least one electrical contact connection from the contact location to at least one of the terminal contacts is produced via the respective contact passages.

Abstract: A method of manufacturing a magnetic tunnel junction device, in which a stack (1) comprising two electrode layers (3, 7) and a barrier layer (5) extending in between is formed. One of the electrode layers is structured by means of etching, in which, during etching, a part of this layer is made thinner by removing material until a rest layer (7r) remains. This rest layer is subsequently removed by means of physical etching, in which at least substantially charged particles have a motion energy which is between the sputtering threshold of the magnetic material of the rest layer and the sputtering threshold of the non-magnetic material of the barrier layer. In the relevant method, it is prevented that the electrode layer which is not to be structured is detrimentally influenced during structuring of the other electrode layer.

Abstract: A high-frequency signal from a tape-shaped line section having a surface layer signal lead and surface layer GND lead disposed on both sides thereof is directly inputted to a semiconductor chip via a signal surface layer wiring of a package substrate and through solder bump electrodes. Alternatively, a high-frequency signal from the semiconductor chip is outputted to the outside via the tape-shaped line section in reverse. Owing to the transmission of the high-frequency signal by only a microstrip line at the whole surface layer of the package substrate, the high-frequency signal can be transmitted by only the microstrip line at the surface layer without through vias or the like. Accordingly, the high-frequency signal can be transmitted without a loss in frequency characteristic, and a high-quality high-frequency signal can be transmitted with a reduction in loss at high-frequency transmission.

Abstract: A method for fabricating a bipolar transistor includes forming a vertical sequence of semiconductor layers, forming an implant mask on the last formed semiconductor layer, and implanting dopant ions into a portion of one or more of the semiconductor layers. The sequence of semiconductor layers includes a collector layer, a base layer that is in contact with the collector layer, and an emitter layer that is in contact with the base layer. The implanting uses a process in which the implant mask stops dopant ions from penetrating into a portion of the sequence of layers.

Abstract: An insulating film (12) is formed on a substrate (11), and an aperture (121) is formed in the prescribed position on the surface of the insulating film (12) perpendicular to such surface, and an amorphous silicon film (13) having a prescribed thickness is formed on the insulating film (12). Subsequently, the amorphous silicon film (13) is changed to a polycrystalline silicon film (13) by a solid-phase growth through a heat treatment. The polycrystalline silicon film (13) is irradiated by a laser under a prescribed condition, and the polycrystalline silicon inside the bottom part of the aperture (121) is maintained in an unmelted state while other parts of the polycrystalline silicon film are completely melted, so that the unmelted polycrystalline silicon can be used as a crystal nucleus for crystal growth, and the area around the aperture (121) in the polycrystalline silicon film is changed to a silicon film in a substantially single crystal state.

Abstract: A magnetic memory cell includes first and second magneto-resistive devices connected in series. The first and second magneto-resistive devices have sense layers with different coercivities. Magnetic Random Access Memory (MRAM) devices may include arrays of these memory cells.

Abstract: A high-frequency signal from a tape-shaped line section having a surface layer signal lead and surface layer GND lead disposed on both sides thereof is directly inputted to a semiconductor chip via a signal surface layer wiring of a package substrate and through solder bump electrodes. Alternatively, a high-frequency signal from the semiconductor chip is outputted to the outside via the tape-shaped line section in reverse. Owing to the transmission of the high-frequency signal by only a microstrip line at the whole surface layer of the package substrate, the high-frequency signal can be transmitted by only the microstrip line at the surface layer without through vias or the like. Accordingly, the high-frequency signal can be transmitted without a loss in frequency characteristic, and a high-quality high-frequency signal can be transmitted with a reduction in loss at high-frequency transmission.

Abstract: The present invention provides a semiconductor device in which a V-groove for holding an optical fiber and an alignment groove for adjusting the distance between the optical fiber and an optical element chip are formed in an optical fiber packaging region on the upper face of a semiconductor substrate, and an optical element chip is packaged in an optical element packaging region on the upper face of the semiconductor substrate so that its optical axis matches the direction in which the V-groove extends. A semiconductor integrated circuit is formed on the lower face of the semiconductor substrate. Through holes are provided in the optical element packaging region of the semiconductor substrate, passing from its upper face to its lower face, and the optical element chip and the semiconductor integrated circuit are connected via the through holes.

Abstract: The invention relates to an apparatus and method for improving AC coupling between adjacent signal traces and between plane splits and signals spanning plane splits on circuit boards. A circuit board includes adjacent conductive means and an oxide means interposed there between. The oxide means is a copper oxide, e.g., cupric or cuprous oxide. In one embodiment, the adjacent conductive means are adjacent voltage reference planes with a split interposed between the conductive means. The copper oxide fills the split. In another embodiment, the adjacent conductive means are differential signal traces. The copper oxide fills a gap between the differential signal traces. The copper oxide is a non-conductive material with an increased dielectric constant as compared to other common dielectric materials used as fillers. The increased dielectric constant increases capacitance, in turn, increasing AC coupling.

Abstract: A route to the fabrication of electronic devices is provided, in which the devices consist of two crossed wires sandwiching an electrically addressable molecular species. The approach is extremely simple and inexpensive to implement, and scales from wire dimensions of several micrometers down to nanometer-scale dimensions. The device of the present invention can be used to produce crossbar switch arrays, logic devices, memory devices, and communication and signal routing devices. The present invention enables construction of molecular electronic devices on a length scale than can range from micrometers to nanometers via a straightforward and inexpensive chemical assembly procedure. The device is either partially or completely chemically assembled, and the key to the scaling is that the location of the devices on the substrate are defined once the devices have been assembled, not prior to assembly.

Abstract: A light emitting device is constructed on a substrate. The device includes an n-type semiconductor layer in contact with the substrate, an active layer for generating light, the active layer being in electrical contact with the n-type semiconductor layer. A p-type semiconductor layer is in electrical contact with the active layer, and a p-electrode is in electrical contact with the p-type semiconductor layer. The p-electrode includes a layer of silver in contact with the p-type semiconductor layer. A bonding layer is formed overlying the silver layer to make an electrical connection to the silver layer. The silver layer may be thin and transparent or thicker (greater than 20 nm) and reflective.

Abstract: Processes are disclosed which facilitate improved high-density memory circuitry, most preferably dynamic random access memory (DRAM) circuitry. Considerably greater numbers of die sites per wafer are achieved for 6-inch, 8-inch and 12-inch wafers for 4M, 16M, 64M, and 256M integration levels. Further, an integrated circuit includes a semiconductor die, a plurality of functional and operably addressable memory cells arranged in at least one array formed on the semiconductor die, and circuitry formed on the semiconductor die and coupled to the memory cells for permitting data to be written to and read from the memory cells, wherein at least one area of 100 square microns of continuous surface area of the die has at least 170 of the memory cells.

Abstract: A semiconductor device comprises a memory cell array portion and peripheral circuit portion, wherein a first insulation film including elements as main components other than nitrogen fills between the memory cell gate electrodes of the memory cell array portion, the first insulation film is formed as a liner on a sidewall of a peripheral gate electrode of the peripheral circuit portion simultaneously with the memory cell portion, and a second insulation film including nitrogen as the main component is formed on the sidewall of the peripheral gate electrode via the first insulation film, thus enabling not only the formation of the memory cell portion having high reliability, but also the formation of a peripheral circuit with good efficiency, simultaneously, and avoiding gate offset of a peripheral gate.

Abstract: A gate dielectric containing LaAlO3 and method of fabricating a gate dielectric contained LaAlO3 produce a reliable gate dielectric having a thinner equivalent oxide thickness than attainable using SiO2. The LaAlO3 gate dielectrics formed are thermodynamically stable such that these gate dielectrics will have minimal reactions with a silicon substrate or other structures during processing. A LaAlO3 gate dielectric is formed by evaporating Al2O3 at a given rate, evaporating La2O3 at another rate, and controlling the two rates to provide an amorphous film containing LaAlO3 on a transistor body region. The evaporation deposition of the LaAlO3 film is performed using two electron guns to evaporate dry pellets of Al2O3 and La2O3. The two rates for evaporating the materials are selectively chosen to provide a dielectric film composition having a predetermined dielectric constant ranging from the dielectric constant of an Al2O3 film to the dielectric constant of a La2O3 film.

Abstract: A semiconductor element including an electrically insulating substrate, semiconductor layers including first and second semiconductor layers of different conduction types and formed on the electrically insulating substrate, a first electrode formed on the first semiconductor layer, and a second electrode formed on the second semiconductor layer revealed by etching at least the first semiconductor layer, wherein a die-bonding electrode is formed on a side surface of the second electrode, on a side surface of the second semiconductor layer and on a region of from a side surface to a bottom surface of the electrically insulating substrate. Metal-metal contact is formed between the die-bonding electrode and the side surface of the second electrode, so that low-resistance contact is obtained here.

Abstract: This invention provides a method for constructing bridge including fine wires or point contacts producing a quanitized inter-electrode conductance, and provides a method for easily controlling the conductance of this bridge. Further, it aims to provide an electronic element using conductance control due to the bridge, fine wire or point contact formed between the electrodes. These objects are accomplied with an electronic element comprising a first electrode comprising a mixed electroconducting material having ion conductance and electron conductance, and a second electrode comprising an electroconducting substance, wherein the inter-electric conductance can be controlled. In another aspect, this invention is an electronic element formed by a bridge between electrodes, by applying a voltage between the electrodes so that the second electrode is negative with respect to the first electrode and movable ions migrate from the first electrode to the second electrode.

Abstract: Semiconductor devices each having a semiconductor layer (1), a gate insulating film (2), a gate electrode (3), an offset spacer layer (4), and SD extension diffusion layers (6) into which ions have been implanted by using the gate electrode (3) and the offset spacer layer (4) as a mask are formed by varying the film thickness of the offset spacer layer (4) and leakage current values in the respective semiconductor devices are measured. The results of the measurements show that the film thickness value of the offset spacer layer (4) and the leakage current value have a correlation therebetween and that the film thickness value of the offset spacer layer (4) when the leakage current value becomes zero corresponds to the length of the portion of the semiconductor layer (1) extending from under the outer end of the offset spacer layer (4) to the tip end of an impurity diffusion layer.

Abstract: In a method of forming a ferroelectric film according to the present invention, pulsed laser light or pulsed lamp light is applied to an amorphous oxide film formed over a substrate to form microcrystalline nuclei of oxide in the oxide film. A light transmission and/or absorption film is formed over the oxide film. Crystallization of the oxide is performed by applying pulsed laser light or pulsed lamp light from above the light transmission and/or absorption film to form a ferroelectric film.