Abstract: A semiconductor device includes a mount substrate, a high-frequency transmission line provided on a top surface of the mount substrate, and a semiconductor chip mounted on the top surface of the mount substrate in a facedown state in electrical contact with the high-frequency transmission line, wherein there is formed a depression on the top surface of the mount substrate.

Abstract: In a charge pump device, occurrence of a latch up can be prevented and current capacity can be increased. An N-type epitaxial silicon layer is formed on a P-type single crystalline silicon substrate, P-type well regions are formed in the N-type epitaxial silicon layer separated from each other, and P-type lower isolation layers and P-type upper isolation layers are formed between the P-type well regions. Then a charge transfer MOS transistor is formed in each of the P-type well regions. The P-type single crystalline silicon substrate is biased to a ground potential or a negative potential.

Abstract: An optoelectronic device such as an LED or laser which produces spontaneous emission by recombination of carriers (electrons and holes) trapped in Quantum Confinement Regions formed by transverse thickness variations in Quantum Well layers of group III nitrides.

Abstract: The invention relates to an SRAM memory cell, a memory cell arrangement and a method for fabricating a memory cell arrangement. The SRAM memory cell has six vertical transistors, of which four are connected up as flip-flip transistors and two are connected up as switching transistors, four of the vertical transistors being arranged at corners of the rectangular base area.

Abstract: An integrated circuit includes a substrate having an etched surface and a non-etched surface. The etched surface contains circuit elements and the non-etched surface contains a bonding surface. The non-etched surface is located at a predetermined height from the etched surface. Bonding this integrated circuit with another substrate creates a wide-gap between the substrates that is preferably evacuated and hermetically sealed.

Abstract: In an integrated pressure sensor including a semiconductor substrate having a p type single crystal silicon substrate and an n type epitaxial layer of which a portion is etched by electrochemical etching to have a diaphragm, an impurity diffusion layer piercing the n type epitaxial layer at least defining the diaphragm is formed for isolation. An etching wire is formed on the surface of the n type epitaxial layer with insulation and the first end of the etching wire extends to the inside of the surface and connected to the n type epitaxial layer. The second opposite end extends to an edge of the semiconductor substrate. The etching wire does not cross the impurity layer inside the surface of the semiconductor substrate to prevent the etching wire from short-circuiting with the impurity diffusion layer during the electrochemical etching.

Abstract: There is provided a susceptor with a built-in electrode and a manufacturing method therefor, in which there is no danger of corrosive gas or plasma or the like penetrating to the inside of the substrate, which has excellent corrosion resistance and plasma resistance, in which nonconductivity under high temperatures is improved, and in which leakage current does not occur.

Abstract: A serial photonic digital-to-analog converter employs a heterojunction thyristor device configured for optically-controlled sampling/switching to convert a digital word encoded by a serial digital optical data signal (e.g., serial optical bit stream) into a corresponding analog electrical signal. A voltage reference is operably coupled to the electrical input terminal of the heterojunction thyristor device. The voltage reference cooperates with the heterojunction thyristor device to sequentially generate at its electrical output terminal a voltage signal representing contribution of each bit of the digital word encoded in the serial digital optical data signal. A summing network is operably coupled to the electrical output terminal of the device. The summing network sequentially sums contribution of the voltage signal over the sequence of bits to produce an analog electrical signal corresponding to the digital word for output therefrom.

Abstract: A concentrator for detecting biological and/or chemical materials in an environment. The concentrator comprises an engineered superlattice structure having alternating layers of elemental, binary or ternary group III-group V, or group IV-group IV semiconducting materials. A method for detecting biological and/or chemical materials in an environment using the concentrator. The method comprising exposing the concentrator to the biological and/or chemical materials in an environment and activating the superlattice structure optically or electrically followed by the detection of the biological and/or chemical materials.

Abstract: A semiconductor chip has standard cells arranged in a plurality of mutually adjacent rows. Each standard cell is connected by a plurality of tracks for connection to other elements of the semiconductor chip and/or terminals of the semiconductor chip. The power supply tracks of the standard cells of at least one row of standard cells are shortened in such a way that the tracks terminate in the region of a standard cell at the edge of the row.

Abstract: A transparent electrode film containing gold for covering the uppermost layer of a group III nitride semiconductor device has a first layer formed on the uppermost layer and not thicker than 15 ?, and a second layer formed on the first layer and containing gold. The first layer contains a first metal having an ionization potential lower than that of gold, and the second layer further contains a second metal having an ionization potential lower than that of gold.

Abstract: Disclosed is a semiconductor device, such as a semiconductor memory device, having structure wherein invasion of minority carriers from the semiconductor substrate into components of the device, formed on the substrate, can be avoided. The semiconductor memory device can be an SRAM or DRAM, for example, and includes a memory array and peripheral circuit on a substrate. In one aspect of the present invention, a buried layer of the same conductivity type as that of the substrate, but with a higher impurity concentration than that of the substrate, is provided beneath at least one of the peripheral circuit and memory array. A further region can extend from the buried layer, for example, to the surface of the semiconductor substrate, the buried layer and further region in combination acting as a shield to prevent minority carriers from penetrating to the device elements.

Abstract: A magnetic memory cell includes first and second magneto-resistive devices connected in series. The first and second magneto-resistive devices have sense layers with different coercivities. Magnetic Random Access Memory (MRAM) devices may include arrays of these memory cells.

Abstract: An array substrate for a liquid crystal display device includes: a substrate; a gate electrode on the substrate; a gate insulating layer on the gate electrode; a semiconductor layer on the gate insulating layer; source and drain electrodes on the semiconductor layer, the source and drain electrodes including a copper layer as an upper layer and a barrier layer as a lower layer; a first passivation layer on the source and drain electrodes; a second passivation layer on the first passivation layer, the second passivation layer having a drain contact hole through the first passivation layer, the drain contact hole exposing the barrier layer; and a pixel electrode connected to the barrier layer through the drain contact hole.

Abstract: A microelectromechanical device is formed in a silicon semiconductor substrate. A metalization layer is formed on a glass wafer. A metal cap layer is then formed on the metalization layer, such that combined layers have a small surface work function that is less than approximately 5.17 eV. The semiconductor substrate is anodically bonded to the glass wafer, and then etched to remove silicon from the structures without significant excess etching of the microelectromechanical device, thus maintaining good control over critical dimensions of the microelectromechanical device.

Abstract: A low-k precursor reactant compound containing silicon and carbon atoms is flowed into a CVD reaction chamber. High-frequency radio-frequency power is applied to form a plasma. Preferably, the reaction chamber is part of a dual-frequency PECVD apparatus, and low-frequency radio-frequency power is applied to the reaction chamber. Reactive components formed in the plasma react to form low-dielectric-constant silicon carbide (SiC) on a substrate surface. A low-k precursor is characterized by one of: a silicon atom and a carbon—carbon triple bond; a silicon atom and a carbon—carbon double bond; a silicon—silicon bond; or a silicon atom and a tertiary carbon group.

Abstract: A method of manufacturing a wafer level package includes forming a semiconductor wafer including semiconductor chips, and forming a package body on the sides of each semiconductor chip. The package body is formed by forming a space between each semiconductor chip and potting a package material in the space, which can be a mold resin. The wafer is then separated into separate semiconductor chips by cutting through the package body.

Abstract: A method of sensing radiation in a pixel includes applying a transfer clock signal, applying a pixel reset clock signal, and applying a pixel reset voltage. The applying a transfer clock signal applies the transfer clock signal to a gate electrode of a transfer gate transistor. The applying a pixel reset clock signal applies the pixel reset clock signal to a gate electrode of the pixel reset transistor. The applying a pixel reset voltage applies the pixel reset voltage to a drain of the pixel reset transistor. The method further includes switching the transfer clock signal to a high state, switching the pixel reset clock signal to a high state, switching the pixel reset voltage to a low state, switching the pixel reset voltage to a high state, and switching the pixel reset clock signal to a low state at a beginning of an integration cycle.

Abstract: The semiconductor laser device has the lower clad layer, active layer, upper clad layer, contact layer, the insulating film, and the positive electrode sequentially formed on the semiconductor substrate. The upper clad layer, the contact layer and the insulating film form the ridge. The positive electrode covers the upper and side faces of the ridge. The thickness of the positive electrode on the upper and side faces of the ridge is preferably substantially the same and it is not less than 150 nm.

Abstract: A multi-layer dielectric layer structure for a semiconductor device. The multi-layer dielectric layer structure comprises a silicate interface layer having a dielectric constant greater than that of silicon nitride and a high-k dielectric layer overlying the silicate interface layer. The high-k dielectric layer comprises one or more ordered pairs of first and second layers. With the present invention, the dielectric constant of the high-k dielectric layer can be optimized while improving interface characteristics. With a higher crystallization temperature realized by forming the multi-layer structure, each of whose layers is not more than the critical thickness, leakage current can be reduced, thereby improving device performance.