Patents Examined by Douglas Menz
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Patent number: 10062701Abstract: The present invention provides a SRAM unit cell which includes a semiconductor substrate, six transistors, a first well, two first doped regions and two second doped regions. The transistors are disposed on the semiconductor substrate, and include a first gate line and a second gate line. The first well is disposed in the semiconductor substrate, and the first well has a first conductive type, wherein the first gate line and the second gate line extend onto the first well. The first doped regions are disposed in the first well at two sides of the first gate line, and the second doped regions are disposed in the first well at two sides of the second gate line.Type: GrantFiled: November 24, 2016Date of Patent: August 28, 2018Assignee: UNITED MICROELECTRONICS CORP.Inventors: Wanxun He, Su Xing
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Patent number: 10056460Abstract: A semiconductor device includes: a semiconductor layer; a first insulating film which covers a surface of the semiconductor layer; a first adhering film which is formed on a surface of the first insulating film and contains a carbonyl group; and a second insulating film which covers a surface of the first adhering film and has a lower dielectric constant than the first insulating film.Type: GrantFiled: August 15, 2016Date of Patent: August 21, 2018Assignee: FUJITSU LIMITEDInventors: Shirou Ozaki, Naoya Okamoto
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Patent number: 10056377Abstract: Methods of forming a VFET SRAM or logic device having a sub-fin level metal routing layer connected to a gate of one transistor pair and to the bottom S/D of another transistor pair and resulting device are provided. Embodiments include pairs of fins formed on a substrate; a bottom S/D layer patterned on the substrate around the fins; conformal liner layers formed over the substrate; a ILD formed over a liner layer; a metal routing layer formed between the pairs of fins on the liner layer between the first pair and on the bottom S/D layer between at least the second pair, an upper surface formed below the active fin portion; a GAA formed on the dielectric spacer around each fin of the first pair; and a bottom S/D contact xc or a dedicated xc formed on the metal routing layer adjacent to the GAA or through the GAA, respectively.Type: GrantFiled: October 17, 2017Date of Patent: August 21, 2018Assignee: GLOBALFOUNDRIES INC.Inventors: Steven Bentley, Bipul C. Paul
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Patent number: 10056443Abstract: An electronic device may have a flexible portion that allows the device to be folded. The device may have a flexible display. The flexible display may have edge portions that are joined along a flexible middle portion. The flexible middle portion may overlap a bend axis and may be bent about the bend axis. Flexibility enhancement regions may be formed in a backing layer, polarizer layer, organic-light-emitting display layer, and other display layers to enhance flexibility for the middle portion. The device may have a display with a flexible tail that is bent about a bend axis. Metal trace on the flexible display may include metal trace strips that serve as power lines. Flexibility enhancement regions such as slot-shaped openings or other openings may be formed in the metal trace strips to enhance flexibility.Type: GrantFiled: August 30, 2016Date of Patent: August 21, 2018Assignee: Apple Inc.Inventors: Terry C. Shyu, Paul S. Drzaic, Zhen Zhang
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Patent number: 10038167Abstract: An organic light emitting device is described. In certain embodiments, the device has a transparent substrate, a transparent grid layer disposed over the substrate, and an OLED disposed over the grid layer. The OLED can include an anode, a cathode, and at least one organic layer between the anode and cathode. A refractive index of the transparent grid layer is less than or equal to a refractive index of the transparent substrate. In certain embodiments, the at least one organic layer includes an electron transport layer having a thickness of at least 50 nm. In certain embodiments, the refractive index of the transparent grid layer is less than n=1.20, or in certain embodiments, less than n=1.05. Methods of manufacturing an organic light emitting device are also described.Type: GrantFiled: January 8, 2016Date of Patent: July 31, 2018Assignee: The Regents of the University of MichiganInventors: Stephen R. Forrest, Yue Qu, Michael Slootsky
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Patent number: 10038156Abstract: A broad-band photodetector utilizes perovskite hybrid material and quantum dots as light harvesters. In particular, the photodetector is configured so that the structural defects on the surface of a quantum dot layer are passivated with perovskite hybrid material. As a result, the trap states on the surface of the quantum dot material is reduced, allowing leakage currents in the quantum dot material to be significantly reduced. As such, the photodetector is able to achieve broad-band operation, with enhanced photoresponsitivity and detectivity.Type: GrantFiled: August 30, 2016Date of Patent: July 31, 2018Assignee: The University of AkronInventors: Xiong Gong, Chang Liu
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Patent number: 10030818Abstract: A liquid-flow monitoring device (10) arranged to monitor the flow of liquid in a conduit. The device (10) comprises sampling means (20), processing means (30) and data storage means (40). The sampling means is arranged to receive data substantially continuously from a sensor (12) indicative of at least one variable sensed by the sensor (12) indicative of fluid flow in a conduit and to sample the data to produce a stream of sampled data. The processing means (30) is arranged to process the stream of sampled data to extract at least one sub-sampled stream therefrom, the sub-sampled stream comprising a plurality of data sets, each data set being a statistical subset of the stream of sampled data over a respective data-set period. The data storage means (40) is arranged to store the at least one sub-sampled stream.Type: GrantFiled: November 28, 2013Date of Patent: July 24, 2018Assignee: IMPERIAL INNOVATIONS LIMITEDInventors: Asher John Hoskins, Ivan Iordanov Stoianov
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Patent number: 10032706Abstract: A package substrate includes a substrate including a circuit region, a dummy region surrounding the circuit region, and a lower circuit pattern at the dummy region, the circuit region including unit regions arranged in a matrix shape, and solders on the lower circuit pattern, at least one of the solders electrically connected to the lower circuit pattern.Type: GrantFiled: August 15, 2016Date of Patent: July 24, 2018Assignee: Samsung Electronics Co., Ltd.Inventors: JinGyu Kim, Taehun Kim, JiSun Hong, Byungmoon Bae, Se-Ho You
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Patent number: 10034360Abstract: A computing unit (10) and a method are provided. The method comprises obtaining data being indicative of operational statuses and geographic positions of a plurality of street devices (11), and obtaining region description data for a region in which the street devices are located. Further, the geographic positions and operational statuses of the street devices are correlated with the region description data.Type: GrantFiled: December 2, 2013Date of Patent: July 24, 2018Assignee: PHILIPS LIGHTING HOLDING B.V.Inventors: Yuan Shu, Alexandre Georgievich Sinitsyn, Ingrid Christina Maria Flinsenberg, Yi Qiang Yu
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Patent number: 10026921Abstract: Provided is a display device including: a base material; a display region over the base material; a wiring over the base material, the wiring extending from the display region to an outside of the display region; and a pair of metal films over the base material, where the wiring is located between the pair of metal films in a plane view. The display region may be positioned between the pair of metal films, and the wiring and the pair of metal films may exist in the same layer.Type: GrantFiled: January 13, 2017Date of Patent: July 17, 2018Assignee: Japan Display Inc.Inventors: Naohisa Andou, Kazuto Tsuruoka
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Patent number: 10020382Abstract: The present disclosure proposes a method of manufacturing a low temperature poly-silicon array substrate, an array substrate and a display panel. The method includes: disposing a substrate, and forming a buffer layer on the substrate; depositing first gas mixture and doped ionized gas by using vapor deposition to form a doped amorphous silicon thin film on the buffer layer; depositing second gas mixture by using vapor deposition to dehydrogenate the amorphous silicon thin film; performing an annealing treatment to the amorphous silicon thin film being dehydrogenated to diffuse dopant ions so as to form a polysilicon layer; and patterning the polysilicon layer.Type: GrantFiled: September 18, 2016Date of Patent: July 10, 2018Assignee: Wuhan China Star Optoelectronics Technology Co., LtdInventors: Xiaodan Hao, Wanting Yin
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Patent number: 10014385Abstract: The thickness of an insulating film, which will serve as an offset spacer film and is formed in an offset monitor region, is managed as the thickness of an offset spacer film formed over the side wall surface of a gate electrode of an SOTB transistor STR, etc. When the measured thickness is within the tolerance of a standard thickness, standard implantation energy and a standard dose amount are set. When the measured thickness is smaller than the standard thickness, implantation energy and a dose amount, which are respectively lower than the standard values thereof, are set. When the measured thickness is larger than the standard thickness, implantation energy and a dose amount, which are respectively higher than the standard values thereof, are set.Type: GrantFiled: September 27, 2017Date of Patent: July 3, 2018Assignee: Renesas Electronics CorporationInventor: Hideki Makiyama
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Patent number: 10014312Abstract: A semiconductor device including a memory cell featuring a first gate insulating film over a semiconductor substrate, a control gate electrode over the first gate insulating film, a second gate insulating film over the substrate and a side wall of the control gate electrode, a memory gate electrode over the second gate insulating film arranged adjacent with the control gate electrode through the second gate insulating film, first and second semiconductor regions in the substrate positioned on a control gate electrode side and a memory gate side, respectively, the second gate insulating film featuring a first film over the substrate, a charge storage film over the first film and a third film over the second film, the first film having a first portion between the substrate and memory gate electrode and a thickness greater than that of a second portion between the control gate electrode and the memory gate electrode.Type: GrantFiled: August 15, 2017Date of Patent: July 3, 2018Assignee: RENESAS ELECTRONICS CORPORATIONInventor: Shoji Shukuri
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Patent number: 10008556Abstract: An organic light-emitting display device includes a substrate including a display area and a peripheral area surrounding the display area. The display area includes a plurality of pixel regions including a plurality of pixels including pixel electrodes and non-pixel regions between the pixel regions. The pixel electrodes are spaced apart from each other, with a pixel-defining layer above the plurality of pixel electrodes and exposing the plurality of pixel electrodes. A plurality of intermediate layers respectively above the plurality of pixel electrodes include an emission layer. A plurality of opposite electrodes respectively face the plurality of pixel electrodes and are spaced apart from each other. A plurality of connection electrodes that connect the plurality of opposite electrodes are in the non-pixel regions. A power line electrically connected to at least one of the plurality of connection electrodes is in the peripheral area.Type: GrantFiled: August 24, 2016Date of Patent: June 26, 2018Assignee: Samsung Display Co., Ltd.Inventor: Jiyoung Choung
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Patent number: 10002938Abstract: Energy bands of a thin film containing molecular clusters are tuned by controlling the size and the charge of the clusters during thin film deposition. Using atomic layer deposition, an ionic cluster film is formed in the gate region of a nanometer-scale transistor to adjust the threshold voltage, and a neutral cluster film is formed in the source and drain regions to adjust contact resistance. A work function semiconductor material such as a silver bromide or a lanthanum oxide is deposited so as to include clusters of different sizes such as dimers, trimers, and tetramers, formed from isolated monomers. A type of Atomic Layer Deposition system is used to deposit on semiconductor wafers molecular clusters to form thin film junctions having selected energy gaps. A beam of ions contains different ionic clusters which are then selected for deposition by passing the beam through a filter in which different apertures select clusters based on size and orientation.Type: GrantFiled: August 20, 2014Date of Patent: June 19, 2018Assignee: STMICROELECTRONICS, INC.Inventor: John H. Zhang
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Patent number: 10001579Abstract: A high-frequency electromagnetic induction system includes a frequency generator coupled to a transmitter coil, a receiver coil coupled to a processor and a high frequency and polarizability data profile for an object of interest. The high frequency and polarizability data profile includes a data object having an array of frequency values and magnetic polarizability values, which are obtained from the object of interest and processed by the processor. Also described is a method for populating the high frequency and polarizability data profile.Type: GrantFiled: March 18, 2015Date of Patent: June 19, 2018Assignee: The United States of America as Represented by the Secretary of the ArmyInventor: Benjamin E Barrowes
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Patent number: 10002912Abstract: An organic light emitting device includes four sub-organic light emitting devices. The first device includes a first anode, a first common light emitting portion, and a first sub-light emitting portion. The second device includes a second anode, a second common light emitting portion, a first auxiliary layer, and a second sub-light emitting portion. The third device includes a third anode and a third common light emitting portion. The fourth device includes a fourth anode, a fourth common light emitting portion, and a light emitting layer emitting a first light. The first and second sub-light emitting portions have an integral structure and emit second light. The first, second, third, and fourth common light emitting portions have an integral structure and emit third light having a wavelength longer than a wavelength of at least one of the first or second lights.Type: GrantFiled: August 30, 2016Date of Patent: June 19, 2018Assignee: Samsung Display Co., Ltd.Inventors: Aree Song, Byeong-hee Won, Wonsang Park, Jongin Baek
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Patent number: 9991474Abstract: An organic light emitting display device includes a first substrate, a pixel structure, a second substrate, a reflective member, and a light transmitting member. The first substrate includes a plurality of pixel regions. Each of the pixel regions has sub-pixel regions and a reflective region surrounding the sub-pixel regions. The pixel structure is disposed in each of the sub-pixel regions on the first substrate. The second substrate is disposed on the pixel structure. The reflective member has an opening disposed in each of the sub-pixel regions, and is disposed in the reflective region of the second substrate. The light transmitting member covers the opening of the reflective member and partially overlaps the reflective member. The light transmitting member blocks ultraviolet rays and transmits a predetermined light.Type: GrantFiled: August 24, 2016Date of Patent: June 5, 2018Assignee: SAMSUNG DISPLAY CO., LTD.Inventors: Min-Soo Kim, Ho-Jin Yoon, Mu-Gyeom Kim, Byoung-Ki Kim, Valeriy Prushinskiy, Dae-Woo Lee, Yun-Mo Chung
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Patent number: 9983449Abstract: A liquid crystal display device includes a TFT substrate and a counter substrate with liquid crystal sandwiched therebetween. The TFT substrate has scanning lines 10 extending in a first direction and arrayed in a second direction and video signal lines 20 extending in the second direction and arrayed in the first direction. The TFT substrate has a display area 500 in which TFT pixels are arrayed in a matrix pattern, and a frame area 600 surrounding the display area. In the frame area 600, common bus wires 521 are formed in the same layer and with the same material as the video signal lines 20 and are impressed with a common voltage. Dummy TFTs are formed in a layer under the common bus wires 521. The scanning lines 10, extending over the frame area 600, are divided outside the display area and are interconnected by bridging wires 170.Type: GrantFiled: May 25, 2017Date of Patent: May 29, 2018Assignee: Japan Display Inc.Inventors: Motoharu Miyamoto, Atsuhiro Katayama
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Patent number: 9983323Abstract: Systems, methods, and computer-readable media for determining a velocity model. The method includes receiving a first velocity model having a first symmetry approximation of a media of a subterranean domain, receiving seismic data representing a subterranean formation, and determining, by operation of a processor, a second velocity model having a second symmetry approximation of the media, the second symmetry approximation being less symmetric than the first symmetry approximation. The second velocity model is determined based on an estimate of residual moveout as a function of azimuth and one or more differentials that relate one or more changes in residual moveout as a function of azimuth to one or more orthorhombic parameters. The method also including migrating the seismic data using the second velocity model.Type: GrantFiled: January 13, 2016Date of Patent: May 29, 2018Assignee: Schlumberger Technology CorporatonInventors: Sribharath Kainkaryam, David Nichols, Robert Bloor, Marvin Decker