Patents Examined by Duc T Doan
  • Patent number: 8356142
    Abstract: A memory controller for non-sequentially prefetching data for a processor of a computer system. The memory controller performs a method including the step of storing a plurality of address pairs in a table data structure, wherein the address pairs include a first address and a second address. The first address and the second address are non-sequential as fetched by a processor of a computer system. The address pairs are prioritized in accordance with a frequency of use for each of the address pairs. A system memory of the computer system is accessed and a plurality of cache lines corresponding to the address pairs are stored in a prefetch cache. Upon a cache hit during a subsequent access by the processor, data is transferred from the cache lines stored in the prefetch cache to the processor.
    Type: Grant
    Filed: November 12, 2003
    Date of Patent: January 15, 2013
    Assignee: Nvidia Corporation
    Inventor: Radoslav Danilak
  • Patent number: 8140797
    Abstract: An integrated circuit having an on-chip access right manager to grant or deny access to a memory segment to a peripheral device such as a CPU (Central Processing Unit), DSP (Digital Signal Processor) or DMA (Direct Memory Access) unit according to predetermined access rights upon reception of a read instruction from the peripheral device, and an on-chip lock connected to a memory data bus, the lock being controllable by the access right manager to block access to a logical one or zero set on each memory data bus wires as long as the access to the memory segment is not granted. Upon reception of the read instruction from the peripheral device, the integrated circuit is configured to start both the process of setting, by the on chip memory, of either a logical one or a logical zero on each of the wires of the memo data bus, as well as the process of granting or refusing the access to the memory segment by the on-chip access right manager to the peripheral device.
    Type: Grant
    Filed: June 28, 2006
    Date of Patent: March 20, 2012
    Assignee: NXP B.V.
    Inventors: Cedrick Robini, Sylvain Duvillard
  • Patent number: 8037240
    Abstract: A system and method for providing reversed backup operation for keeping local hard drives in a stand-by (non-spinning) mode thereby extending the life of local hard drives and reducing power consumption, heat and noise produced by the local drives. The present invention uses remote storage systems as primary storage systems when the network connectivity and its bandwidth are sufficient so that the local hard disk can stay in the stand-by mode. If the network connectivity is unavailable or insufficient to handle the data flow, the local hard disk is spun up and temporarily used as the primary storage for reads and writes. When necessary and possible, the data on both storage locations is synchronized.
    Type: Grant
    Filed: October 24, 2007
    Date of Patent: October 11, 2011
    Assignee: International Business Machines Corporation
    Inventor: Nikolai Joukov
  • Patent number: 8024523
    Abstract: A technique for determining a data window size allows a set of predicted blocks to be transmitted along with requested blocks. A stream enabled application executing in a virtual execution environment may use the blocks when needed.
    Type: Grant
    Filed: April 4, 2008
    Date of Patent: September 20, 2011
    Assignee: Endeavors Technologies, Inc.
    Inventors: Jeffrey de Vries, Arthur Shingen Hitomi
  • Patent number: 8015378
    Abstract: A method of updating memory content stored in a memory of a processing device, the memory comprising a plurality of addressable memory blocks, the memory content being protected by a current integrity protection data item stored in the processing device, the method comprising determining a first subset of memory blocks that require an update, and a second subset of memory blocks that remain unchanged by said updating; calculating, as parallel processes, a first and a second integrity protection data item over the memory blocks; wherein the first integrity protection data item is calculated over the current memory contents of the first and second subsets of memory blocks; and wherein the second integrity protection data item is calculated over the current memory contents of the second subset of memory blocks and the updated memory block contents of the first subset of memory blocks.
    Type: Grant
    Filed: December 20, 2005
    Date of Patent: September 6, 2011
    Assignee: Telefonaktiebolaget L M Ericsson (Publ)
    Inventor: Christian Gehrmann
  • Patent number: 7991964
    Abstract: A cache architecture to increase communication throughput and reduce stalls due to coherence protocol dependencies. More particularly, embodiments of the invention include multiple cache agents that each communication with the same protocol agent. In one embodiment, a pre-coherence channel couples the cache agents to the protocol agent to enable the protocol agent to receive events corresponding to cache operations from the cache agents to maintain ordering with respect to the cache operation events.
    Type: Grant
    Filed: June 24, 2010
    Date of Patent: August 2, 2011
    Assignee: Intel Corporation
    Inventor: Benjamin Tsien
  • Patent number: 7991965
    Abstract: A technique for using memory attributes to relay information to a program or other agent. More particularly, embodiments of the invention relate to using memory attribute bits to check various memory properties in an efficient manner.
    Type: Grant
    Filed: February 7, 2006
    Date of Patent: August 2, 2011
    Assignee: Intel Corporation
    Inventors: Quinn A. Jacobson, Anne Weinberger Bracy, Hong Wang, John P. Shen, Per Hammarlund, Matthew C. Merten, Suresh Srinivas, Kshitij A. Doshi, Gautham N. Chinya, Bratin Saha, Ali-Reza Adl-Tabatabai, Gad S. Sheaffer
  • Patent number: 7987332
    Abstract: A method for operating a non-volatile memory storage system is provided. In this method, a queue that is configured to store memory operations associated with two or more types of memory operations. Here, memory operations are associated with the maintenance of the non-volatile memory storage system. A memory operation is scheduled for execution in response to an event and the memory operation is stored in the queue.
    Type: Grant
    Filed: March 21, 2007
    Date of Patent: July 26, 2011
    Assignee: SanDisk Technologies Inc.
    Inventor: Shai Traister
  • Patent number: 7987334
    Abstract: An apparatus, system, and method are disclosed for adjusting memory hold time. A detection module detects a hold time violation for a memory. An adjustment module increases a first voltage of a voltage controller in response to the hold time violation. The voltage controller supplies electrical current at the first voltage to a memory controller and at a reference voltage to the memory. The first and reference voltages are set independently.
    Type: Grant
    Filed: February 28, 2008
    Date of Patent: July 26, 2011
    Assignee: International Business Machines Corporation
    Inventor: WenWei Wang
  • Patent number: 7984240
    Abstract: A method, apparatus and program product enable memory compression for a system including processor with directly attached memory. A memory expander microchip facilitates memory compression while attached to a processor. The memory expander microchip may provide additional bandwidth and memory capacity for the system to enable memory compression in a manner that does not burden the attached processor or associated operating system. The processor may store uncompressed data in its lower latency, directly attached memory, while the memory attached to the memory expander may store either or both compressed and uncompressed data.
    Type: Grant
    Filed: March 4, 2008
    Date of Patent: July 19, 2011
    Assignee: International Business Machines Corporation
    Inventor: John M. Borkenhagen
  • Patent number: 7984254
    Abstract: Snapshots that are consistent across a group of data objects are generated. The snapshots are initiated by a coordinator, which transmits a sequence of commands to each storage node hosting a data object within a group of data objects. The first command prepares a data object for a snapshot. After a data object has been successfully prepared, an acknowledgment is sent to the coordinator. Once all appropriate acknowledgments are received, the coordinator sends a command to confirm that a snapshot has been created for each data object in the respective group. After receiving this confirmation, the coordinator takes action to confirm or record the successful completion of the group-consistent snapshot.
    Type: Grant
    Filed: April 4, 2008
    Date of Patent: July 19, 2011
    Assignee: VMware, Inc.
    Inventors: Christos Karamanolis, Matthew Benjamin Amdur, Patrick William Penzias Dirks
  • Patent number: 7979655
    Abstract: A method, computer program product and system for dynamically optimizing the limit and the thresholds of a write cache for a storage adapter connected to storage devices, includes measuring continually an overall locality of data in the write cache for the storage devices, calculating the limit of the write cache dynamically for each storage device using the overall locality and a device-related information, and calculating the threshold of the write cache dynamically for each storage device by combining a fair amount and a device-related additional amount.
    Type: Grant
    Filed: March 4, 2008
    Date of Patent: July 12, 2011
    Assignee: International Business Machines Corporation
    Inventors: Joseph Roger Edwards, Robert Edward Galbraith, Adrian Cuenin Gerhard, Timothy James Larson, William Joseph Maitland, Jr.
  • Patent number: 7962694
    Abstract: In an embodiment, a method is provided. The method of this embodiment provides receiving a request for data from a processor of a plurality of processors, determining a cache entry location based, at least in part, on the request, storing the data in a cache corresponding to the processor at the cache entry location, and storing a coherency record corresponding to the data in a snoop filter in accordance with one of the following, if there is a cache miss: at the cache entry location of a corresponding affinity in the snoop filter if the cache entry location is found in the corresponding affinity, or at a derived cache entry location of the corresponding affinity if the cache entry location is not found in the corresponding affinity.
    Type: Grant
    Filed: December 14, 2006
    Date of Patent: June 14, 2011
    Assignee: Intel Corporation
    Inventors: Meenakshisundaram R. Chinthamani, Kai Cheng, Malcolm Mandviwalla, Bahaa Fahim, Keith R. Pflederer
  • Patent number: 7962714
    Abstract: Systems and methods for protecting data in a tiered storage system are provided. The storage system comprises a management server, a media management component connected to the management server, a plurality of storage media connected to the media management component, and a data source connected to the media management component. Source data is copied from a source to a buffer to produce intermediate data. The intermediate data is copied to both a first and second medium to produce a primary and auxiliary copy, respectively. An auxiliary copy may be made from another auxiliary copy. An auxiliary copy may also be made from a primary copy right before the primary copy is pruned.
    Type: Grant
    Filed: December 19, 2008
    Date of Patent: June 14, 2011
    Assignee: CommVault Systems, Inc.
    Inventors: Arun Prasad Amarendran, Manoj Kumar Vijayan Retnamma, Anand Prahlad, Parag Gokhale, Jun Lu
  • Patent number: 7962703
    Abstract: Techniques for improving dirty page logging are disclosed. In one particular exemplary embodiment, the techniques may be realized as a method for memory logging comprising the steps of determining for one or more pages of memory if the pages of memory are likely to be modified in a subsequent epoch, performing a first operation on the pages of memory that are likely to be modified in a subsequent epoch, and performing a second operation on the pages of memory that are not likely to be modified in a subsequent epoch, wherein the first operation and the second operation are dissimilar.
    Type: Grant
    Filed: August 8, 2007
    Date of Patent: June 14, 2011
    Assignee: Symantec Corporation
    Inventors: Dharmesh R. Shah, Anurag Agarwal, Ankur Arora, Nitin Madan, Sureshbabu Basavayya, Ashish Puri, Srikanth S. Mahabalarao, Gurbir Singh Dhaliwal
  • Patent number: 7958319
    Abstract: A method and apparatus for accelerating transactional execution. Barriers associated with shared memory lines referenced by memory accesses within a transaction are only invoked/executed the first time the shared memory lines are accessed within a transaction. Hardware support, such as a transaction field/transaction bits, are provided to determine if an access is the first access to a shared memory line during a pendancy of a transaction. Additionally, in an aggressive operational mode version numbers representing versions of elements stored in shared memory lines are not stored and validated upon commitment to save on validation costs. Moreover, even in a cautious mode, that stores version numbers to enable validation, validation costs may not be incurred, if eviction of accessed shared memory lines do not occur during execution of the transaction.
    Type: Grant
    Filed: October 29, 2007
    Date of Patent: June 7, 2011
    Assignee: Intel Corporation
    Inventors: Bratin Saha, Ali-Reza Adl-Tabatabai, Quinn A. Jacobson
  • Patent number: 7958307
    Abstract: Methods and systems are provided for associating a storage system component, e.g. a server, client, machine, sub-client, or other storage system component, with one or more other storage system components into a group. Storage preferences are defined for the group which is automatically associated with each component in the group. The storage preferences define how storage operations are to be performed on the storage system components.
    Type: Grant
    Filed: December 3, 2010
    Date of Patent: June 7, 2011
    Assignee: CommVault Systems, Inc.
    Inventors: Srinivas Kavuri, Anand Prahlad, Anand Vibhor, Parag Gokhale
  • Patent number: 7958310
    Abstract: An apparatus, system, and method are disclosed for selecting a space efficient repository. A cache receives write data. A destage module destages the data sequentially to a coarse grained repository such as a stride level repository and destages a directory entry for the data to a coarse grained directory such as a stride level directory if the data satisfies a repository policy. In addition, the destage module destages the data to a fine grained repository such as a track level repository overwriting an existing data instance and destages the directory entry to a fine grained directory such as a track level directory if the data does not satisfy the repository policy.
    Type: Grant
    Filed: February 27, 2008
    Date of Patent: June 7, 2011
    Assignee: International Business Machines Corporation
    Inventors: Michael Thomas Benhase, Shachar Fienblit, Yu-Cheng Hsu, Matthew Joseph Kalos
  • Patent number: 7953936
    Abstract: According to one embodiment of the invention, an apparatus having one or more cache agents and a protocol agent is disclosed. The protocol agent is coupled to the one or more cache agents to receive events corresponding to cache operations from the one or more cache agents to maintain ordering with respect to the cache operation events. The protocol agent includes a structure to handle conflict resolution.
    Type: Grant
    Filed: October 14, 2008
    Date of Patent: May 31, 2011
    Assignee: Intel Corporation
    Inventor: Benjamin Tsien
  • Patent number: 7945760
    Abstract: Techniques are described for efficient reordering of data and performing data exchanges within a register file or memory, or in general, any device storing data that is accessible through a set of addressable locations. In one technique, an address translator is placed in the path of all or a selected set of address busses to a storage device to provide a programmable translating of the storage device addresses. An effect of this translation is that the data stored in one pattern may be accessed and stored in another pattern or accessed, processed and stored in another pattern. The address translation operation may be carried out in a single cycle, does not involve the physical movement of data in swap operations, allows data to effectively be ordered more efficiently for algorithmic processing and therefore saves power. Address translation functions are shown to be useful for vector operations and a new type of storage unit using built in address translation functions is presented.
    Type: Grant
    Filed: April 1, 2004
    Date of Patent: May 17, 2011
    Assignee: Altera Corporation
    Inventors: Edwin Franklin Barry, Gerald George Pechanek