Patents Examined by Duc T Doan
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Patent number: 7805570Abstract: The subject application is directed to a system and method for secure document processing. A removable storage, such as a flash drive, magnetic storage, IC card, is installed in document processing device. A selected document processing operation, such as copying, scanning, and the like, is then performed. Data files resultant from the selected document processing operations are directed to the removable storage for being stored temporary, instead of being sent to the storage inherent to the document processing device. Data files temporary stored in the removable storage are then deleted.Type: GrantFiled: September 7, 2007Date of Patent: September 28, 2010Assignees: Kabushiki Kaisha Toshiba, Toshiba Tec Kabushiki KaishaInventor: Fabio M. Gava
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Patent number: 7805568Abstract: An apparatus for data storage includes a cluster of NFS servers. Each server has network ports for incoming file system requests and cluster traffic between servers. The apparatus includes a plurality of storage arrays in communication with the servers. The servers utilize a striped file system for storing data. A method for data storage. A method for establishing storage for a file. A method for removing a file from storage. A method for reading data in a file. A method for writing data in a file.Type: GrantFiled: October 31, 2008Date of Patent: September 28, 2010Assignee: Spinnaker Networks, LLCInventors: Michael L. Kazar, Richard N. Sanzi, Jr.
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Patent number: 7797493Abstract: The present invention relates to a data processing device (10) comprising a processing unit (12) and a memory unit (14), and to a method for controlling operation of a memory unit (14) of a data processing device. The memory unit (14) comprises a main memory (16), a low- level cache memory (20.2), which is directly connected to the processing unit (12) and adapted to hold all pixels of a currently active sliding search area for reading access by the processing unit (12), a high-level cache memory (18), which is connected between the low-level cache memory and the frame memory, and a first pre-fetch buffer (20.1), which is connected between the high-level cache memory and the low- level cache memory and which is adapted to hold one search-area column or one search-area line of pixel blocks, depending on the scan direction and scan order followed by the processing unit. Reading and fetching functionalities are decoupled in the memory unit (14).Type: GrantFiled: February 13, 2006Date of Patent: September 14, 2010Assignee: Koninklijke Philips Electronics N.V.Inventors: Harm Johannes Antonius Maria Peters, Ramanathan Sethuraman, Gerard Veldman, Patrick Peter Elizabeth Meuwissen
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Patent number: 7797500Abstract: Described are techniques for migrating data from a source device to a target device. A source device descriptor of the source device including source device geometry parameters and a source device partition definition structure is received. Target device geometry parameters are received. The source partition definition structure is translated and a mapped partition definition structure in accordance with the target device geometry parameters is generated. A target device descriptor including the target device geometry parameters and the mapped partition definition structure is generated. The target device descriptor is stored on the target device. Data for one or more partitions of the source device is migrated to the target device.Type: GrantFiled: March 21, 2007Date of Patent: September 14, 2010Assignee: EMC CorporationInventors: Jeffrey A. Lewis, Anestis Panidis, Arieh Don, Pei-Ching Hwang, Michael E. Specht, Andrew Ralich
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Patent number: 7788448Abstract: A cache system includes a cache memory dedicated to service a number of sequencers with sequencer code. A number of cache managers are defined to direct placement of sequencer code portions into the cache memory. Also, each of the number of cache managers is defined to provide sequencer code from the cache memory to a respectively assigned sequencer. An external memory is defined to store a complete version of the sequencer code. A direct memory access (DMA) engine is defined to write sequencer code portions from the external memory to the cache memory, in accordance with direction from the number of cache managers.Type: GrantFiled: January 19, 2007Date of Patent: August 31, 2010Assignee: PMC-Sierra US, Inc.Inventor: Marc Spitzer
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Patent number: 7788451Abstract: A memory hub includes first and second link interfaces for coupling to respective data busses, a data path coupled to the first and second link interfaces and through which data is transferred between the first and second link interfaces, and further includes a write bypass circuit coupled to the data path to couple write data on the data path and temporarily store the write data to allow read data to be transferred through the data path while the write data is temporarily stored. A method for writing data to a memory location in a memory system is provided which includes accessing read data in the memory system, providing write data to the memory system, and coupling the write data to a register for temporary storage. The write data is recoupled to the memory bus and written to the memory location following provision of the read data.Type: GrantFiled: February 5, 2004Date of Patent: August 31, 2010Assignee: Micron Technology, Inc.Inventors: Douglas A. Larson, Jeffrey J. Cronin
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Patent number: 7783846Abstract: A method is disclosed to operate a memory device. The method includes, prior to overwriting a first unit of data at a location in a memory device with a second unit of data, determining if more energy is required to write the second unit of data than to write the second unit of data with at least one sub-unit thereof having bits that are inverted. If it is determined that less energy is required to write the second unit of data with the at least one sub-unit thereof having bits that are inverted, the method further includes overwriting the first unit of data with a modified second unit of data with the at least one sub-unit thereof having bits that are inverted, in conjunction with writing at least one bit memory for indicating a location in the modified unit of data of the sub-unit of data having the inverted bits.Type: GrantFiled: August 9, 2007Date of Patent: August 24, 2010Assignee: International Business Machines CorporationInventor: Timothy Chainer
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Patent number: 7779204Abstract: A removable media storage network environment employs a media management system for managing a removable media system on behalf of client applications, and a media management agent to enhance the management of the removable media system by the media management system. The media management agent operates to determine an operational state of the removable media system, and to enhance an availability and a performance of the removable media system as managed by a media management system, wherein one or more one error recovery techniques are conditionally initiated based on the determined operational state of the removable media system and wherein the media management system is conditionally reconfigured based on the determined operational state of the removable media system.Type: GrantFiled: October 24, 2008Date of Patent: August 17, 2010Assignee: International Business Machines CorporationInventors: Juergen Deicke, Leonard George Jesionowski, Wolfgang Mueller
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Patent number: 7769956Abstract: A cache architecture to increase communication throughput and reduce stalls due to coherence protocol dependencies. More particularly, embodiments of the invention include multiple cache agents that each communication with the same protocol agent. In one embodiment, a pre-coherence channel couples the cache agents to the protocol agent to enable the protocol agent to receive events corresponding to cache operations from the cache agents to maintain ordering with respect to the cache operation events.Type: GrantFiled: September 7, 2005Date of Patent: August 3, 2010Assignee: Intel CorporationInventor: Benjamin Tsien
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Patent number: 7765381Abstract: A system may include a plurality of nodes. Each node may include an active device and a memory subsystem coupled to the active device. An active device in one of the nodes is configured to generate a global address that identifies a coherency unit and associated translation information identifying a translation function to be performed on the global address. A memory subsystem included in the node is configured to perform the translation function identified by the translation information on the global address to generate a physical address of the coherency unit within the memory subsystem. An additional memory subsystem included in an additional one of the nodes is configured to store the translation information identifying the translation function used in the node. In response to a request for access to the coherency unit, the additional memory subsystem is configured to send the translation information to the node.Type: GrantFiled: April 2, 2004Date of Patent: July 27, 2010Assignee: Oracle America, Inc.Inventors: Anders Landin, Erik E. Hagersten
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Patent number: 7765377Abstract: A method to write information to one or more information storage media disposed in a data storage and retrieval system comprising host adapters capable of data compression and information storage devices capable of data compression. The method establishes a storage medium usage threshold and determines the actual storage media usage level for the data storage and retrieval system. The method then determines if the actual storage media usage level is greater than the storage medium usage threshold. If the actual storage media usage level is greater than said storage medium usage threshold, then the method enables use of information storage device data compression. Alternatively, if the actual storage media usage level is not greater than said storage medium usage threshold, then the method disables use of information storage device data compression.Type: GrantFiled: May 8, 2003Date of Patent: July 27, 2010Assignee: International Business Machines CorporationInventors: Cheryl M. Friauf, Gregory T. Kishi, Jonathan W. Peake
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Patent number: 7761659Abstract: Method and apparatus for wave flushing cached writeback data to a storage array. A cache manager operates to initiate a wave flushing operation whereby sets of writeback data in a cache memory are sequentially written to each of a plurality of logical groups radially concentric with respect to the storage medium. During the wave flushing operation, a write transducer is radially advanced across the medium in a single radial direction across boundaries between immediately adjacent groups. The write operations thus form a traveling wave across the medium, analogous to a wave in a sports stadium formed by spectators standing up and sitting down in turn. Each logical group preferably corresponds to a selected transducer seek range, such as an associated RAID stripe. Seeks are preferably bi-directional within each group, and uni-directional between adjacent groups. A dwell time (service time interval) for each group can be constant, or adaptively adjusted.Type: GrantFiled: June 30, 2006Date of Patent: July 20, 2010Assignee: Seagate Technology LLCInventors: Clark E. Lubbers, Michael D. Walker
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Patent number: 7761649Abstract: A storage system is provided with an ASIC having an interconnect selectively coupling a plurality of dedicated purpose function controllers in the ASIC to a policy processor, via a list manager in the ASIC communicating on a peripheral device bus to which the policy processor is connected, and an event ring buffer to which all transaction requests from each of the plurality of function controllers to the policy processor are collectively posted in real time.Type: GrantFiled: June 30, 2007Date of Patent: July 20, 2010Assignee: Seagate Technology LLCInventor: Clark Edward Lubbers
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Patent number: 7761650Abstract: A dual ported active-active array controller apparatus is provided having a first policy processor partnered with a first ISP having a first plurality of dedicated purpose FCs, a second policy processor partnered with a second ISP having a second plurality of dedicated purpose FCs, a communication bus interconnecting the ISPs, and programming instructions stored in memory and executed by the array controller to maintain the first policy processor in top level control of transaction requests from both the first plurality of FCs and the second plurality of FCs that are associated with network input/output (I/O) commands directed to a storage logical unit number (LUN) which the first ISP is a logical unit master of.Type: GrantFiled: June 30, 2007Date of Patent: July 20, 2010Assignee: Seagate Technology LLCInventors: Clark Edward Lubbers, Michael Dean Walker, James Francis McCarty
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Patent number: 7757060Abstract: For reducing wake latency time of an information handling system (IHS), a non-volatile random access memory (NVRAM) of the IHS is updated every time a main random access memory (RAM) of the IHS is changed or refreshed, thereby saving memory data. In response to a sleep event, the IHS is transitioned from a higher activity state to a sleep state, thereby removing power provided to the RAM. In response to a resume event, the IHS is restored back to the higher activity state from the sleep state. Upon restoring the power to the RAM, contents of the NVRAM are copied to the RAM to restore the memory data in a virtually instant manner.Type: GrantFiled: September 11, 2006Date of Patent: July 13, 2010Assignee: Dell Products L.P.Inventors: Adolfo Sandor Montero, Craig Lawrence Chaiken, Andrew Thomas Sultenfuss
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Patent number: 7752397Abstract: In a cache coherency protocol multiple conflict phases may be utilized to resolve a data request conflict condition. The multiple conflict phases may avoid buffering or stalling conflict resolution, which may reduce system inefficiencies.Type: GrantFiled: January 9, 2009Date of Patent: July 6, 2010Assignee: Intel CorporationInventors: Aaron Spink, Robert Beers
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Patent number: 7752385Abstract: A high density storage enclosure houses first and second pluralities of hard disk drives (HDDs). The enclosure may be partitioned into a plurality of virtual enclosures, the first plurality of HDDs being associated with a first virtual enclosure and the second plurality of HDDs being associated with a second virtual enclosure. Configuration of the storage enclosure is performed by an SES processor in the storage enclosure accessing configuration parameters received from an external configuration unit coupled to the storage enclosure. The virtual enclosures may be configured as two (or more) independent virtual enclosures on two (or more) independent fabrics or may be configured in a trunked manner. Power supplies and cooling blowers in the storage enclosure may also be partitioned and assigned to be managed by SES processors in the virtual enclosures.Type: GrantFiled: September 7, 2006Date of Patent: July 6, 2010Assignee: International Business Machines CorporationInventors: John C. Elliott, Robert A. Kubo, Gregg S. Lucas
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Patent number: 7739475Abstract: A system and method for updating dirty data of designated raw device is applied in Linux system. A format of a command parameter for updating the dirty data of the designated raw device is determined, to obtain the command parameter with the correct format and transmit it into the Kernel of the Linux system. Then, a data structure of the designated raw device is sought based on the command parameter, to obtain a fast search tree of the designated raw device. Finally, all dirty data pages of the designated raw device are found by the fast search tree, and then are updated into a magnetic disk in a synchronous or asynchronous manner. Therefore, the dirty data of an individual raw device can be updated and written into the magnetic disk without interrupting the normal operation of the system, hereby ensuring secure, convenient, and highly efficient update of the dirty data.Type: GrantFiled: October 24, 2007Date of Patent: June 15, 2010Assignee: Inventec CorporationInventors: Lei He, Tom Chen, Win-Harn Liu
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Patent number: 7739474Abstract: A system and method for unifying access to a physical memory by operations using virtual addresses of the same virtual address space are provided. The operations may be generated by at least one central processing unit (CPU operations) and/or by at least one IO device (IO operations). The system may include a bus arranged to transfer data and virtual addresses of the same virtual address space from the central processing unit (CPU) and the IO device to a unified memory management unit (UMMU), a unified memory management unit (UMMU) arranged to translate the virtual addresses to physical addresses, and to protect the physical memory from illegal access attempts of the CPU operations and the IO operations. The system may further include a memory controller arranged to manage access to the physical memory. The access is done by using physical addresses.Type: GrantFiled: February 7, 2006Date of Patent: June 15, 2010Assignee: International Business Machines CorporationInventors: Antonius Paulus Engbersen, Julian Satran, Edi Shmueli, Thomas Basil Smith, III
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Patent number: 7734861Abstract: Easily implemented randomization within a flash memory EEPROM reduces the NAND string resistance effect, program disturbs, user read disturbs, and floating gate to floating gate coupling that result from repeated and long term storage of specific data patterns. The randomization may be code generated pseudo randomization or user driven randomization in different embodiments. User driven commands, the timing of which cannot be predicted may be used to trigger and achieve a high level of randomization. Randomly altering the encoding scheme of the data prevents repeated and long term storage of specific data patterns. Even if a user wishes to store the same information for long periods, or to repeatedly store it, it will be randomly encoded with different encoding schemes, and the data pattern will therefore be varied.Type: GrantFiled: September 8, 2006Date of Patent: June 8, 2010Assignee: Sandisk CorporationInventors: Yan Li, Yupin Kawing Fong, Nima Mokhlesi