Abstract: Techniques are described for efficient reordering of data and performing data exchanges within a register file or memory, or in general, any device storing data that is accessible through a set of addressable locations. In one technique, an address translator is placed in the path of all or a selected set of address busses to a storage device to provide a programmable translating of the storage device addresses. An effect of this translation is that the data stored in one pattern may be accessed and stored in another pattern or accessed, processed and stored in another pattern. The address translation operation may be carried out in a single cycle, does not involve the physical movement of data in swap operations, allows data to effectively be ordered more efficiently for algorithmic processing and therefore saves power. Address translation functions are shown to be useful for vector operations and a new type of storage unit using built in address translation functions is presented.

Abstract: Time and frequency de-interleaving of interleaved data in an Integrated Services Digital Broadcasting Terrestrial (ISDB-T) receiver includes exactly one random access memory (RAM) buffer in the ISDB-T receiver that performs both time and frequency de-interleaving of the interleaved data and a buffer address calculation module for generating buffer address in the buffer. The system performs memory sharing of the time and frequency de-interleaver for ISDB-T receivers and reduces the memory size required for performing de-interleaving in an ISDB-T receiver and combines the frequency and time de-interleaver buffers into one RAM thereby reducing the memory size.

Abstract: Flow identification value masks are identified based on, and used to mask a flow identification value associated with packets in a router, packet switching or computer system, any other device. These masks may be specified in access control lists or using any other mechanism, and typically are added to an associative memory or other mechanism keyed on their corresponding flow identification values for performing fast lookup operations. A lookup operation is performed based on the flow identification value associated with a particular packet to identify the correspond mask, which is then used to produce a masked flow identification value, and based on which, a value is updated in a data structure and/or other processing of the packet is performed.

Abstract: The system is composed of the storage apparatuses with dynamic chunk allocation capabilities, the centralized management computer. Some storage apparatuses have the extra HDDs or volumes for providing extra capacity (extra chunks), which are concealed by a secret key. The storage apparatus with the closed segment has the key management program and key management table. The centralized management computer has the storage on demand management program, the pending request table, the priority table and the master key table. The storage apparatus may connect to the other storage apparatuses for sharing the extra capacities in the closed segment. The storage apparatus issues the chunk addition request to the centralized management computer. The centralized management computer provides a key according to the priority table and the master key table.

Abstract: The systems and methods described herein include among other things, systems for providing a block level data storage service. More particularly, the systems and methods of the invention provide a block level data storage service that provides differentiated pools of storage on a single storage device. To this end, the systems and methods described herein leverage the different performance characteristics across the logical block name (LBN) space of the storage device (or devices). These different performance characteristics may be exploited to support two or more classes of storage on a single device.

Abstract: A predictive model is used to populate a cache in a videogame system. The predictive model takes as an input a sequence of file sections that have been requested for the associated videogame thus far. The predictive model then returns the names or indicators of one or more file sections that will likely be requested in the future along with a probability that those file sections will be requested. A cache driver executing in the background of the videogame system may then use the predictive model to reduced load times during the execution of a videogame by retrieving the predicted file sections from the optical disk and placing them in a cache during periods of low CPU activity.

Abstract: The disclosed embodiments relate to a security module and a method of operating a security module. The method may comprise the acts of detecting a second security module, determining whether a key associated with the second security module is available to the first security module, and obtaining the key associated with the second security module if the key associated with the second security module is not available to the first security module. The security module may comprise a detector that is adapted to detect another security module and determine whether one of a plurality of keys is associated with the other security module, and a device that obtains at least one key associated with the other security module if the one of the plurality of keys is not associated with the other security module.

Abstract: A method, apparatus and program product enable associativity operations for system including a processor having directly attached memory. A memory expander microchip facilitates concurrent memory access while attached to a processor. Associativity may have particular application in the context of accessing a data cache, which may be present on the memory expander microchip or memory in communication with the microchip. The memory expander microchip and associated memory channels may provide additional bandwidth and memory capacity for the system to enable associativity in a manner that does not burden the attached processor or associated operating system. Bandwidth and memory may be dynamically allocated to optimize associativity and applicable operating ratios.

Abstract: A method, computer program product and computer system for maintaining write cache and parity update footprint coherency in a multiple storage adaptor configuration for storage adaptors in a storage subsystem, which includes providing atomic updating of the storage adaptors and the attached disk drives, enabling runtime addition and runtime subtraction of a storage adaptor in the multiple storage adaptor configuration, and maintaining write cache and parity update footprint coherency using atomic updating, runtime addition and runtime subtraction of a storage adaptor.

Abstract: In one embodiment, the present invention includes a translation lookaside buffer (TLB) having storage locations each including a priority indicator field to store a priority level associated with an agent that requested storage of the data in the TLB, and an identifier field to store an identifier of the agent, where the TLB is apportioned according to a plurality of priority levels. Other embodiments are described and claimed.

Abstract: A computer-implemented method of cache replacement includes steps of: determining whether each cache block in a cache memory is a read or a write block; augmenting metadata associated with each cache block with an indicator of the type of access; receiving an access request resulting in a cache miss, the cache miss indicating that a cache block will need to be replaced; examining the indicator in the metadata of each cache block for determining a probability that said cache block will be replaced; and selecting for replacement the cache block with the highest probability of replacement.

Abstract: Described is a technology by which a secondary nonvolatile storage (e.g., a flash memory device) maintains a copy of the changes made to a hard drive after a data backup operation. The backup changes are combinable with backed up data to recreate a hard drive state, whereby changes after the last backup are not lost, e.g., if the hard drive fails. The backup change data may maintain the changes at the block (e.g., allocation unit) level corresponding to hard drive blocks, or at the file level, corresponding to files or parts of files on the hard drive. The backup changes may be filtered, so that only certain data (e.g., user data) are maintained as backup change data. Read requests can be satisfied by reading data from the backup change data, or from a performance (e.g., disk) cache that may also reside on the nonvolatile storage.

Abstract: Provided are a method, system, and article of manufacture for copying storage. Data sent from a first storage unit is synchronously copied at a second storage unit. The copied data is sent asynchronously from the second storage unit to a third storage unit.

Abstract: A high-capacity memory subsystem architecture utilizes multiple memory modules arranged in one or more clusters, each attached to a respective hub which in turn is attached to a memory controller. Within a cluster, data is interleaved so that each data access command accesses all modules of the cluster. The hub communicates with the memory modules at a lower bus frequency, but the distributing of data among multiple modules enables the cluster to maintain the composite data rate of the memory-controller-to-hub bus. Preferably, the memory system employs buffered memory chips having dual-mode operation, one of which supports a cluster configuration in which data is interleaved and the communications buses operate at reduced bus width and/or reduced bus frequency to match the level of interleaving.

Abstract: A system and method for fixing data inconsistency between an original dataset stored on a source storage server and a mirror of the original dataset stored on a destination storage server is provided. The method determines whether the mirror is consistent with the original dataset by comparing metadata describing the original dataset with metadata describing the mirror. If the mirror is inconsistent with the original dataset, corresponding block(s) of the original dataset is/are requested and received from the source storage server. The mirror is then fixed according to the received block(s).

Abstract: A dual-mode memory chip supports a first operation mode in which received data access commands contain chip select data to identify the chip addressed by the command, and control logic in the memory chip determines whether the command is addressed to the chip, and a second operation mode in which the received data access command addresses a set of multiple chips. Preferably, the first mode supports a daisy-chained configuration of memory chips. Preferably the second mode supports a hierarchical interleaved memory subsystem, in which each addressable set of chips is configured as a tree, command and write data being propagated down the tree, the number of chips increasing at each succeeding level of the tree.

Abstract: There is provided a storage management system capable of utilizing division management with enhanced flexibility and of enhancing security of the entire system, by providing functions by program products in each division unit of a storage subsystem. The storage management system has a program-product management table stored in a shared memory in the storage subsystem and showing presence or absence of the program products, which provide management functions of respective resources to respective SLPRs. At the time of executing the management functions by the program products in the SLPRs of users in accordance with instructions from the users, the storage management system is referred to and execution of the management function having no program product is restricted.

Abstract: A personal sensing device that may be used for storing personal data and sensed data arbitrates and prioritizes competing requests for memory access from sensing, wireless, and wired interfaces. The personal sensing device enables power efficiency with burst-writes to the memory at higher data rates then an incoming sensor data stream without risk of data loss. Sensing operations coordinated by reconfigurable control logic are partitioned from storage operations coordinated by a multi-port memory controller. The interface between the functional partitioning uses message passing, status/control registers and buffering to reduce or eliminate system interdependencies.

Abstract: Employing a coherency controller having a primary path and at least one secondary path to at least one interconnection network is disclosed. A method of an embodiment of the invention is performed by the coherency controller of a node. The coherency controller determines whether transactions are being properly sent to other nodes of a plurality of nodes of which the node is a part via a primary path. In response to determining that the transactions are not being properly sent to the at least one interconnection network via the primary path, the coherency controller instead sends the transactions to the other nodes via a secondary path.

Abstract: Example embodiments of an IOMMU with translation request management and methods for managing translation requests are generally described herein. Other example embodiments may be described and claimed. In some example embodiments, the IOMMU comprises one or more reorder buffers. Each reorder buffer may be associated with one I/O device and may be used to queue pending translation requests for the associated I/O device. A translation request received from a requesting I/O device may be stored in a reorder buffer associated with the requesting I/O device when the translation request is unable to be serviced or when there are one or more pending translation requests in the reorder buffer.