Abstract: Techniques for processing an access request and updating a storage system are provided. For instance, a method comprises: receiving an access request for an object associated with a storage system, the storage system including a plurality of physical nodes, each of the plurality of physical nodes including at least one set of virtual units, each set of virtual units including at least one virtual unit; determining, from a plurality of sets of virtual units included in the plurality of physical nodes of the storage system, a target set of virtual units associated with the object; and determining, from the target set of virtual units, a target virtual unit corresponding to the object. With the technical solution of the present disclosure, not only a set of virtual units on a physical node may be easily split and merged, but also huge computing resources that need to be allocated may be saved, so better user experience may be brought about at a lower cost.

Abstract: Copy-on-Write (CoW) snapshots share data on disk for extents that have not been overwritten, which allows for efficient use of disk space. A chain of snapshots may be created, where each snapshot corresponds to a point in time. A sequence of snapshots may be copied by rebuilding each snapshot for the destination volume based on the source volume, resulting in memory usage at the destination volume substantially similar to the memory usage of the snapshot sequence at the source volume.

Abstract: Embodiments for replicating data in a disaggregated computing system. A memory pool is allocated, where the memory pool includes allocated memory elements at a first site and allocated memory elements at a second site. The allocated memory elements are mapped at the first site to the allocated memory elements at the second site. A replication operation is initiated to mirror data stored within the allocated memory elements at the first site to the allocated memory elements at the second site. The allocated memory elements at the first site are directly connected through an independent networking connection to the allocated memory elements at the second site such that the replication operation is processed exclusively through compute resources at the first site.

Abstract: A storage controller is configured to perform a full stride destage, a strip destage, and an individual track destage. A machine learning module receives a plurality of inputs corresponding to a plurality of factors that affect performance of data transfer operations and preservation of drive life in the storage controller. In response to receiving the inputs, the machine learning module generates a first output, a second output, and a third output that indicate a preference measure for the full stride destage, the strip destage, and the individual track destage respectively.

Abstract: A first score corresponding to a full stride destage, a second score corresponding to a strip destage, and a third score corresponding to an individual track destage are computed, wherein the first score, the second score, and the third score are computed for a group of Input/Output (I/O) operations based on a first metric and a second metric, wherein the first metric is configured to affect a performance of data transfers, and wherein the second metric is configured to affect a drive life. A determination is made of a type of destage to perform based on the first score, the second score, and the third score.

Abstract: Techniques for automatically recreating data removed from storage are disclosed. A request to access data at a first storage location is received. It is determined, based on a catalog and using a computer processor, that the data has been removed from the first storage location. In response the data at the first storage location is automatically recreated using the computer processor. The recreating includes identifying a second storage location for the data, based on the catalog, retrieving the data from the second storage location, and storing the data at the first storage location. The catalog is updated to reflect recreating the data at the first storage location.

Abstract: A memory controller includes, in one implementation, a host interface, a memory interface, and a flash translation layer (FTL). The FTL is configured to receive a request from a host device to store data in a zone of a solid-state memory. The FTL is also configured to determine a zone reset rate classification as one of a hot classification, a cold classification, and a normal classification. The FTL is further configured to allocate the zone to a memory die with the fewest free die blocks when the zone reset rate classification is the hot classification. The FTL is also configured to allocate the zone to a memory die with the most free die blocks when the zone reset rate classification is the cold classification. The FTL is further configured to send the data to the memory die for storage therein.

Abstract: A method for performing data-compression management in a storage server may include: receiving data from a host device; performing entropy detection on a plurality of sets of partial data to generate entropy detection values of the plurality of sets of partial data, respectively; classifying the plurality of sets of partial data according to the entropy detection values of the plurality of sets of partial data, respectively, to perform data compression on at least one portion of the plurality of sets of partial data through a plurality of data compression modules, respectively, wherein the plurality of data compression modules correspond to different compression capabilities, respectively; and storing the plurality of sets of partial data into at least one storage device of the storage server and recording address mapping information of the plurality of sets of partial data, respectively. An associated apparatus is also provided.

Abstract: In a data storage control device for writing data into a first memory that is non-volatile memory, an information receipt unit receives voltage-related information from a power source control device. A condition determination unit determines whether a voltage condition is satisfied. When the condition determination unit determines that the voltage condition is satisfied during execution of a writing process, a memory controller determines whether a predetermined storage condition is satisfied. When the storage condition is not satisfied, the memory controller executes a first response process of withdrawing writing residual data into the first memory but setting a validity flag as invalid. When the storage condition is satisfied, the memory controller executes a second response process of writing the residual data into the first memory.

Abstract: Apparatuses for computing are disclosed herein. An apparatus may include a set of data reduction modules to perform data reduction operations on sets of (key, value) data pairs to reduce an amount of values associated with a shared key, wherein the (key, value) data pairs are stored in a plurality of queues located in a plurality of solid state drives remote from the apparatus. The apparatus may further include a memory access module, communicably coupled to the set of data reduction modules, to directly transfer individual ones of the sets of queued (key, value) data pairs from the plurality of remote solid state drives through remote random access of the solid state drives, via a network, without using intermediate staging storage. Other embodiments may be disclosed or claimed.

Abstract: A processor includes a prediction table, a prediction logic circuit, and a prediction verification circuit. The prediction table has a plurality of sets, each of the sets has a hot way number, at least one warm way number, and at least one confidence value corresponding to the at least one warm way number. The prediction logic circuit generates a prediction result by predicting if the at least one warm way number is an opened way. The prediction verification circuit generates a correct/incorrect information according to the prediction result, and generates an update information according to the correct/incorrect information. The prediction verification circuit updates the hot way number, the at least one warm way number and the at least one confidence value of the at least one warm way number according to the update information.

Abstract: A non-limiting example computer-implemented method includes receiving instructions to switch an operational context of a dynamic address translation (DAT) structure to a new operational context. It is determined if context switching has been enabled within the DAT structure. Based on determining that context switching is enabled, it is determined if the new operational context of the DAT structure is different than a current operational context of the DAT structure. It is chosen whether to switch to a full operational context based on the new operational context being different than the current operational context. If the full operational context is used, a full space DAT structure is set up and a private space bit is set to OFF, and if the full operational context is not used, a partial space DAT structure is set up and the private space bit is set to ON.

Abstract: One embodiment includes a system comprising a repository configured to store objects, an object cache configured to cache objects retrieved from the repository by a node, a memory configured to store a broadcast cache invalidation queue accessible by a plurality of nodes and an invalidation status, a processor coupled to the memory and a computer readable medium storing computer-executable instructions.

Abstract: Systems, apparatuses, and methods for performing coherence processing and memory cache processing in parallel are disclosed. A system includes a communication fabric and a plurality of dual-processing pipelines. Each dual-processing pipeline includes a coherence processing pipeline and a memory cache processing pipeline. The communication fabric forwards a transaction to a given dual-processing pipeline, with the communication fabric selecting the given dual-processing pipeline, from the plurality of dual-processing pipelines, based on a hash of the address of the transaction. The given dual-processing pipeline performs a duplicate tag lookup in parallel with a memory cache tag lookup for the transaction. By performing the duplicate tag lookup and the memory cache tag lookup in a parallel fashion rather than in a serial fashion, latency and power consumption are reduced while performance is enhanced.

Abstract: An operating method of a storage device which includes a first nonvolatile memory device and a second nonvolatile memory device includes detecting sudden power-off, suspending an operation being performed in the first nonvolatile memory device, in response to the detected sudden power-off, writing suspension information about the suspended operation into the second nonvolatile memory device, and performing a block management operation on the first nonvolatile memory device based on the suspension information written into the second nonvolatile memory device, in power-up after the sudden power-off.

Abstract: Examples may include a deduplication system threshold based on an amount of wear of a storage device. Examples may obtain an indication of an amount of wear experienced by at least one storage device storing a plurality of container indexes of a deduplication system, and may adjust a threshold of the deduplication system based on the amount of wear.

Abstract: A method for managing logical-to-physical (L2P) mappings in a memory subsystem is described. The method includes updating, by a set of processing units, an L2P table based on a set of journal pages from the non-volatile memory. The L2P table prior to the update includes a first set of entries from a table snapshot and the table includes a second set of entries following the update from a set of journal pages. Each L2P table entry (1) corresponds to a logical address in a set of logical addresses and (2) includes a physical address of a set of memory components. The set of logical addresses are categorized into zones and each processing unit is assigned to a separate zone such that each processing unit updates the first set of entries based on an assigned zone of a corresponding logical address and each zone includes at least two non-contiguous logical addresses.

Abstract: A memory system, a memory controller and an operating method thereof, capable of reducing the storage capacity of data in relation with map tables, by, in the case where N map entries respectively corresponding to N consecutive physical address regions exist among map entries included in a first map table in a memory device, adding a group map entry indicating a mapping information corresponding to the group of the N number of consecutive physical address regions, to a second map table included in the memory device.

Abstract: A computer-implemented method, according to one embodiment, includes: in response to experiencing a power loss event, resupplying power to NVRAM which includes a write cache. In response to detecting that the NVRAM has experienced a failure event, the NVRAM is temporarily guarded from further use. Moreover, a portion of volatile memory is allocated to serve as a temporary write cache. The allocated portion of volatile memory is also cleared. A determination is made as to whether data is present in the write cache in the NVRAM, and in response to determining that data is present in the write cache, one or more volumes in memory which correspond to the data present in the write cache in the NVRAM are marked as having experienced data loss. Furthermore, a warning is sent which indicates that data loss has been experienced by the one or more marked volumes in the memory.

Abstract: A memory subsystem enables per device addressability (PDA) to target configuration commands to one of multiple memory devices that share a select line or buffer devices that share an enable line. The system includes a host and multiple memory devices that can be coupled over a command bus and a data bus. The devices include a configuration or mode register to store a value to indicate whether PDA enumeration is enabled. When enabled, the host can provide an enumeration identifier (ID) command via the command bus with a signal via the data bus to assign an enumeration ID. After assignment of the enumeration ID, the host can send PDA commands via the command bus with the enumeration ID, without a signal on the data bus. Devices only process PDA commands that match their assigned enumeration ID, enabling the setting of device-specific configuration settings without needing to use the data bus on every PDA command.