Abstract: An in-line (or foreground) approach to obtaining contiguous ranges of free space in a file system of a data storage system that can select windows having blocks suitable for relocation at a time when one or more blocks within the respective windows are freed or de-allocated. By providing the in-line or foreground approach to obtaining contiguous ranges of free space in a file system, a more efficient determination of windows having blocks suitable for relocation can be achieved, thereby conserving processing resources of the data storage system.

Abstract: A storage device includes at least one nonvolatile memory device including a plurality of memory blocks, the nonvolatile memory device configured to store user data and meta data in the plurality of memory blocks, and a device controller configured to control the nonvolatile memory device, to calculate a user cost corresponding to a time of memory accesses to the user data to be performed at garbage collection with respect to each of the plurality of memory blocks, to calculate a meta cost corresponding to a time of memory accesses to the meta data to be performed at the garbage collection with respect to each of the plurality of memory blocks, to select a victim block among the plurality of memory blocks based on the user cost and the meta cost, and to perform the garbage collection on the victim block.

Abstract: Example implementations relate to a capability enforcement processor. In an example, a capability enforcement processor may be interposed between a memory that stores data accessible via capabilities and a system processor that executes processes. The capability enforcement processor intercepts a memory request from the system processor and enforces the memory request based on capability enforcement processor capabilities maintained in per-process capability spaces of the capability enforcement processor.

Abstract: A memory controller controls first and second memory, and includes a control unit. In response to a first write command from a host, which designates a logical address for first data to be written to the first memory, the control unit determines whether mapping of the logical address is presently being managed in a first mode with a first cluster size or a second mode with a second cluster size that is smaller than the first cluster size, changes first mapping data for the logical address stored in a first table in the second memory, from the first cluster size to the second cluster size, if the mapping of the logical address is being managed in the first mode and the first mapping data can be compressed at a ratio lower than a first compression ratio, and writes the first data to a physical address of the first memory.

Abstract: A storage system comprises a plurality of storage devices and an associated storage controller. The storage controller is configured to receive a request to copy a first range of logical addresses to a second range of logical addresses, determine at least one physical block of the storage devices to which the first range of logical addresses is mapped, map the second range of logical addresses to the determined at least one physical block, and add at least one content-based signature associated with the determined at least one physical block to a pending increment data structure that includes content-based signatures corresponding to physical blocks for which an increment of an associated reference count is pending. The storage controller is further configured to execute a pending increment of a reference count associated with a given physical block corresponding to at least one of the content-based signatures in the pending increment data structure.

Abstract: An input data may be received. Memory pages may be identified where each of the memory pages includes one or more cache lines. A first index table that includes cache lines may be generated from the memory pages based on the input data. Subsequently, an output data may be provided based on a particular cache line from the cache lines of the first index table.

Abstract: A read request from a host system can be received. It can be detected that the read request is associated with a pattern of read requests. A requested transfer size associated with the read request can be identified. A size of data to retrieve can be determined. The size of the data can be based on the requested transfer size and a die-level transfer size associated with a die of a memory system.

Abstract: Storage circuitry is provided, that is designed to form part of a memory hierarchy. The storage circuitry comprises receiver circuitry for receiving a request to obtain data from the memory hierarchy. Transfer circuitry causes the data to be stored at a selected destination in response to the request, wherein the selected destination is selected in dependence on at least one selection condition. Tracker circuitry tracks the request while the request is unresolved. If at least one selection condition is met then the destination is the storage circuitry and otherwise the destination is other storage circuitry in the memory hierarchy.

Abstract: A processor circuit includes: multiple processor cores; multiple individual memories; multiple shared memories; multiple memory control circuits; multiple selectors; and a control core; wherein when an address of the read request from the first processor associated with a specific memory control circuit is identical to the transfer source address, the specific memory control circuit controls the transfer data based on the read request to be transferred to the transfer destination address via a specific selector of the multiple selectors in which the transfer selection information is set, wherein, when the control core sets read selection information in each of the multiple selectors, read data is read by one of the first processor core and the first adjacent processor core from the associated shared memory via a specific selector of the multiple selectors in which the read selection information is set.

Abstract: A method of prefetching attribute data from storage for a graphics processing pipeline comprising a cache, and at least one buffer to which data is prefetched from the storage and from which data is made available for storing in the cache. The method comprises retrieving first attribute data from the storage, the first attribute data representative of a first attribute of a first vertex of a plurality of vertices of at least one graphics primitive, identifying the first vertex, and, in response to the identifying, performing a prefetch process. The prefetch process comprises prefetching second attribute data from the storage, the second attribute data representative of a second attribute of the first vertex, the second attribute being different from the first attribute, and storing the second attribute data in a buffer of the at least one buffer.

Abstract: Examples described herein may include migration of data associated with a service to a container. An example method includes creating of a user virtual machine associated with a service and an associated virtual disk storing data associated with running the service, and creating a volume group and an associated storage container at a node of a computing system. The example method further includes storing a cloned version of the virtual disk into the storage container, and, in response to discovery of the cloned version of the virtual disk in the storage container, mounting the cloned version of the virtual disk on the volume group to provide access to clients running the service.

Abstract: A storage controlling apparatus, includes: a memory configured to store a program; and a processor configured to control a plurality of storage devices based on the program, wherein the processor: collects information relating to a data access performed for the plurality of storage devices; and decides performance degradation of a first storage device from among the plurality of storage devices based on a response achievement time period for a first data access request performed for the first storage device, and a response time period average value and a response time period standard deviation which are calculated based on response achievement time periods with respect to a plurality of data access requests performed for the first storage device before the first data access request.

Abstract: A system and method are provided for memory control, having selectively distributed power-on processing. A memory controller executes responsive to a master control operation to actuate a plurality of operational tasks on a memory device. The memory controller includes a first power-on block executable to actuate one or both of initialization and training operations corresponding to the memory device. A PHY portion coupled to the memory controller portion executes to adaptively configure control, address, and data signals for physically compatible passage between the controller portion and memory device. The PHY portion includes a second power-on block executable to actuate one or both of an initialization operation and a training operation corresponding to the memory device. The PHY portion is configured according to the initialization and training operations, wherein each of the initialization and training operations are selectively actuated responsive to one of the power-on blocks.

Abstract: A memory management method for a rewritable non-volatile memory module is provided according to an exemplary embodiment of the disclosure. The memory management method includes: recording sorting information corresponding to a plurality of first physical units of the rewritable non-volatile memory module according to a data storage status of the first physical units; receiving at least one command, and the command is configured to change the data storage status of the first physical units; updating the sorting information according to the command; and copying data stored in at least one physical unit among the first physical units to at least one second physical unit of the rewritable non-volatile memory module according to the updated sorting information.

Abstract: A method and apparatus for using cache size estimations for guiding hot-tier insertion decisions. The method and apparatus include an adaptive management element that determines what accesses of a resource should be logged and the parameters for logging. The determinations are used to configure an adaptive logging element to log only accesses corresponding to the selected resource(s) and to log only those accesses that match the identified parameters. The adaptive management element operates in a feedback loop: first determining what will be logged and second implementing that determination by an adaptive logging element. Upon a triggering event, the process returns to the first determination based on any then current parameters. In some embodiments, the parameters include a size estimate to achieve a given target hit rate (target hit rate size estimate) that is used in generating a score or weighting to identify the highest/best scoring/weighted disk(s) for logging.

Abstract: In a method of operating a data storage device including a non-volatile memory device, which includes a closed memory block and an open memory block, a scan pointer and a map scan information of the open memory block is generated. The scan pointer indicates a page next to a page to which a writing operation is completed. The map scan information includes a logical address information mapped in a page of the open memory block. When the data storage device is recovered from a power loss, the logical address information is read based on the map scan information. An address map is rebuilt based on the read logic address information.

Abstract: A system for increasing data retention time can include a processor to execute code to detect or predict a write event associated with a flash memory. The processor can also control a device to cause a temperature at the flash memory to increase via waste heat in response to the write event. Additionally, the processor can write data to the flash memory at the increased temperature to increase the retention time of the data stored in the flash memory.

Abstract: Predictively selecting subset of disks of a storage system to be spun-up, including providing metadata of data entities stored in the disks of the storage system, estimating the data entity access probabilities for a prediction time window based on the metadata, each data entity access probability being indicative for the probability of access to a certain data entity within the prediction time window, calculating disk access probabilities for a prediction time window based on the estimated probability of access of data entities, each disk access probability being indicative for the probability of access to a certain disk within the prediction time window, estimating the number of disks to be spun-up in a certain prediction time window, dynamically adapting the data entity threshold value and/or the disk access threshold value, selecting a subset of disks to be spun-up in the following prediction time window.

Abstract: A filter comprises interface circuitry, to intercept coherency protocol transactions exchanged between a master device comprising a first cache and an interconnect for managing coherency between the first cache and at least one other cache or other master device. The filter has filtering circuitry for filtering the coherency protocol transactions in dependence on memory access permission data defining which regions of an address space the master device is allowed to access.

Abstract: Aspects of the present disclosure relate to a memory module having a volatile memory, a high speed non-volatile memory, and a non-volatile memory. The memory module can allow write mirroring to the volatile memory and high speed non-volatile memory simultaneously. An I/O request is received. A determination is made whether the I/O request is a write or a read. In response to determining that the I/O request is a read, data included in the high speed non-volatile memory is transferred to the non-volatile memory. In response to determining that the I/O request is a write, at least one location to write data of the write is determined based on decoding bits of the write command. The data of the write can then be written to the at least one location.