Patents Examined by Duy Deo
  • Microneedles with sharpened tips and corresponding method of fabrication
    Patent number: 9526885
    Abstract: Microneedles with sharpened tips are fabricated without any reduction to the shaft diameter below the tip. By sharpening the tip and not the entire length of the microneedle, their mechanical strength is maintained. The microneedles are fabricated out of a wafer substrate using lithography and deep reactive-ion etching (DRIE). By controlling the timing of the DRIE as the photoresist depletes, the sharpness and angle of the tips are controlled.
    Type: Grant
    Filed: March 24, 2014
    Date of Patent: December 27, 2016
    Assignee: University of South Florida
    Inventors: Puneet Khanna, Shekhar Bhansali
  • Etching method
    Patent number: 9530671
    Abstract: An etching method for etching an object to be processed in a processing chamber including a first electrode and a second electrode disposed facing the first electrode and configured to receive the object to be processed thereon is provided that includes steps of intermittently supplying first high frequency power to either the first electrode or the second electrode while supplying second high frequency power lower than the first high frequency power to the second electrode, supplying a process gas containing hydrogen bromide HBr and oxygen O2 into the processing chamber, and etching a poly silicon film deposited on the object to be processed into a mask pattern of a silicon-containing oxide film patterned by a spacer double patterning method by plasma generated from the process gas.
    Type: Grant
    Filed: April 22, 2014
    Date of Patent: December 27, 2016
    Assignee: TOKYO ELECTRON LIMITED
    Inventor: Yoichi Nakahara
  • Method and apparatus for ESC charge control for wafer clamping
    Patent number: 9530626
    Abstract: A plasma processing method and apparatus are provided in which current spikes associated with application of a voltage to an electrostatic chuck (ESC) are minimized or reduced when the processing plasma is present. According to an example, the voltage is applied to the ESC after the processing plasma is struck, however the voltage is ramped or increased in a step-wise manner to achieve the desired final ESC voltage. In an alternate embodiment, the ESC voltage is at least partially applied before striking of the plasma for processing the wafer. By reducing current spikes associated with application of the voltage to the ESC during the presence of the processing plasma, transfer or deposition of particles on the wafer can be reduced.
    Type: Grant
    Filed: July 23, 2015
    Date of Patent: December 27, 2016
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Jason Marion, Sonam Sherpa, Sergey A. Voronin, Alok Ranjan, Yoshio Ishikawa, Takashi Enomoto
  • Method of manufacturing composite crucible
    Patent number: 9527763
    Abstract: A method of manufacturing a composite crucible includes: supplying mullite material powder to an upper region of a mold, and supplying second silica powder to a lower region provided below the upper region while rotating the mold; supplying third silica powder on an inner surface side of a layer made of the mullite material powder and the second silica powder; heating and fusing the mullite material powder, the second silica powder, and the third silica powder to form an opaque vitreous silica layer provided on the outer surface of the crucible, a transparent vitreous silica layer provided on an inner surface side of the crucible, and a mullite reinforcement layer provided on the outer surface side of an upper end portion of the crucible.
    Type: Grant
    Filed: December 27, 2015
    Date of Patent: December 27, 2016
    Assignee: SUMCO CORPORATION
    Inventors: Toshiaki Sudo, Ken Kitahara, Takuma Yoshioka
  • Silicon dry etching method
    Patent number: 9524877
    Abstract: A dry etching method according to the present invention is for etching a silicon layer as a processing target in a processing room, characterized by supplying an iodine heptafluoride-containing etching gas from a gas supply source at a supply pressure of 66 kPa to 0.5 MPa, evacuating the processing room to an internal pressure lower than the supply pressure of the etching gas and, while maintaining the etching gas at the supply pressure, introducing the etching gas into the evacuated processing room so as to etch the silicon layer by the etching gas. It is possible by this dry etching method to etch the silicon upon adiabatic expansion of the etching gas under mild pressure conditions, with no fear of equipment load and equipment cost increase, and achieve good uniformity of in-plane etching amount distribution.
    Type: Grant
    Filed: January 24, 2014
    Date of Patent: December 20, 2016
    Assignee: Central Glass Company, Limited
    Inventors: Akiou Kikuchi, Isamu Mori, Masanori Watari
  • Plasma etching method and plasma etching apparatus
    Patent number: 9524876
    Abstract: Disclosed is a plasma etching method including a deposition process and an etching process. For a processing target object including a base layer and a photoresist having a predetermined pattern which are laminated in sequence, the deposition process deposits a protective layer including silicon and carbon on the photoresist of the processing target object by plasma of a first processing gas including silicon tetrachloride gas, methane gas, and hydrogen gas. The etching process etches the base layer by plasma of a second processing gas using the photoresist including the protective layer deposited thereon, as a mask. The second processing gas is different from the first processing gas.
    Type: Grant
    Filed: May 13, 2015
    Date of Patent: December 20, 2016
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Toru Hisamatsu, Masanobu Honda
  • Method for manufacturing hybrid transparent electrode and hybrid transparent electrode
    Patent number: 9524046
    Abstract: Provided herein is a method for producing a hybrid transparent electrode, the method including filling grooves of a substrate with a conductive metal ink composition; filling the grooves with residue conductive metal ink composition that remains on a surface of the substrate as the grooves are being filled with the conductive metal ink composition to form an electrode pattern; and forming a conductive layer including a conductive material on the electrode pattern.
    Type: Grant
    Filed: May 16, 2014
    Date of Patent: December 20, 2016
    Assignee: INKTEC CO., LTD.
    Inventors: Kwang-Choon Chung, In-Sook Yi, Ji Hoon Yoo, Joonki Seong, Dae sang Han
  • Peroxide-vapor treatment for enhancing photoresist-strip performance and modifying organic films
    Patent number: 9514954
    Abstract: Methods and apparatus for treating an organic film such as photoresist with a hydroxyl-generating compound prior to removing the organic film from a substrate are provided. Treatments include exposure to one or more of hydrogen peroxide vapor and water vapor in a non-plasma environment. In some implementations, conditions are such that condensation on the surface is suppressed. Methods include treating high-dose ion-implantation photoresists and post-plasma doping photoresists with little or no material loss and permit mild plasma removal of the photoresist after treatment.
    Type: Grant
    Filed: June 10, 2014
    Date of Patent: December 6, 2016
    Assignee: Lam Research Corporation
    Inventors: Bayu Atmaja Thedjoisworo, Bradley Jon Jacobs, Ivan Berry, David Cheung
  • Etching method of semiconductor substrate, and method of producing semiconductor device
    Patent number: 9514958
    Abstract: An etching method containing the step of processing a substrate having a first layer containing titanium nitride (TiN) and a second layer containing a transition metal by bringing an etching liquid into contact with the substrate and thereby removing the first layer, wherein the first layer has a surface oxygen content from 0.1 to 10% by mole, and wherein the etching liquid comprises an ammonia compound and an oxidizing agent, and has a pH of from 7 to 14.
    Type: Grant
    Filed: May 27, 2015
    Date of Patent: December 6, 2016
    Assignee: FUJIFILM Corporation
    Inventors: Yoshinori Nishiwaki, Tetsuya Kamimura, Tadashi Inaba, Atsushi Mizutani
  • Method and apparatus for building three-dimensional MEMS elements
    Patent number: 9511995
    Abstract: The disclosure generally relates to method and apparatus for forming three-dimensional MEMS. More specifically, the disclosure relates to a method of controlling out-of-plane buckling in microstructural devices so as to create micro-structures with out-of-plane dimensions which are 1×, 5×, 10×, 100× or 500× the film's thickness or above the surface of the wafer. An exemplary device formed according to the disclosed principles, includes a three dimensional accelerometer having microbridges extending both above and below the wafer surface.
    Type: Grant
    Filed: February 15, 2012
    Date of Patent: December 6, 2016
    Assignee: Massachusetts Institute of Technology
    Inventors: Brian Lee Wardle, Fabio Ferruccio Fachin, Stefan Nikles, Mathew Varghese
  • Multiple exposure treatment for processing a patterning feature
    Patent number: 9512517
    Abstract: A method for processing a substrate may include providing a patterning feature on the substrate, the patterning feature having a sidewall. The method may further include implanting a first ion species into the patterning feature during a first exposure, the first ion species having a first implantation depth; and implanting a second ion species into the patterning feature during a second exposure, the second ion species having a second implantation depth less than the first implantation depth.
    Type: Grant
    Filed: March 12, 2015
    Date of Patent: December 6, 2016
    Assignee: Varian Semiconductor Equipment Associates, Inc.
    Inventors: Tristan Y. Ma, Maureen K. Petterson, John Hautala, Ludovic Godet
  • Metallization inhibitors for plastisol coated plating tools
    Patent number: 9506150
    Abstract: The plastisol coated plating tools are used to secure polymer containing substrates in electroless plating baths during electroless plating of the polymers. To prevent metallization of the plastisol coated plating tools during electroless metallization, compositions of sulfur compounds are applied to the plastisol. After metallization the plastisol coated plating tools may be re-used without the need to strip the unwanted metal from the tools.
    Type: Grant
    Filed: October 1, 2015
    Date of Patent: November 29, 2016
    Inventors: Katharina Weitershaus, Andreas Scheybal, Wan Zhang-Beglinger
  • Method for selective oxide removal
    Patent number: 9502264
    Abstract: A method for removing oxide selective to a material comprising at least silicon and at least nitrogen is disclosed, the method comprising providing in a reactor a structure having a surface comprising a region, wherein said region comprises a material comprising at least silicon and at least nitrogen, providing on said structure an oxide layer overlying at least a part of said region, and removing said oxide layer selective to said material by etching, thereby exposing at least a part of said at least overlaid part of said region, wherein said etching is done only by providing an etchant gas comprising boron, whereby a voltage bias lower than 30 V is applied to the structure.
    Type: Grant
    Filed: August 17, 2015
    Date of Patent: November 22, 2016
    Assignee: IMEC VZW
    Inventors: Eddy Kunnen, Vasile Paraschiv
  • Method for producing SiC substrate
    Patent number: 9502230
    Abstract: A method of manufacturing a SiC substrate of the invention includes at least an oxide film-forming process of forming an oxide film (10) to cover a surface (1a) of the SiC substrate (1); and a planarization process of polishing the SiC substrate (1) from an oxide film side (10) in accordance with a CMP method so as to remove the oxide film (10), and of polishing the surface (1a) of the SiC substrate (1) to planarize the surface (1a).
    Type: Grant
    Filed: November 27, 2013
    Date of Patent: November 22, 2016
    Assignee: SHOWA DENKO K.K.
    Inventors: Yuzo Sasaki, Kenji Suzuki
  • Colloidal silica chemical-mechanical polishing composition
    Patent number: 9499721
    Abstract: A chemical-mechanical polishing composition includes colloidal silica abrasive particles dispersed in a liquid carrier. The colloidal silica abrasive particles include a nitrogen-containing or phosphorus-containing compound incorporated therein such that the particles have a positive charge. The composition may be used to polish a substrate including a silicon oxygen material such as TEOS.
    Type: Grant
    Filed: June 25, 2015
    Date of Patent: November 22, 2016
    Assignee: Cabot Microelectronics Corporation
    Inventors: Steven Grumbine, Jeffrey Dysard, Ernest Shen, Mary Cavanaugh
  • Continuous or semi-continuous biomass wash system for hydrothermal hydrocatalytic conversion
    Patent number: 9492851
    Abstract: A selective removal of metal and its anion species that are detrimental to subsequent hydrothermal hydrocatalytic conversion from the biomass feed in a continuous or semi-continuous manner prior to carrying out catalytic hydrogenation/hydrogenolysis/hydrodeoxygenation of the biomass that does not reduce the effectiveness of the hydrothermal hydrocatalytic treatment while minimizing the amount of water used in the process is provided.
    Type: Grant
    Filed: December 18, 2014
    Date of Patent: November 15, 2016
    Assignee: Shell Oil Company
    Inventors: Joseph Broun Powell, Robert Edward Trepte, Juben Nemchand Chheda
  • Automated vision system for a crystal growth apparatus
    Patent number: 9493888
    Abstract: Various embodiments of a method for producing a crystalline material in a crucible in a crystal growth apparatus are disclosed. The method comprises, in part, the step of monitoring for remaining solid feedstock in a liquid feedstock melt with an automated vision system positioned above the crucible. Alternatively, or in addition, the method comprises the step of monitoring for solidified crystalline material in a partially solidified melt with the automated vision system. A crystal growth apparatus comprising the automated vision system is also disclosed.
    Type: Grant
    Filed: March 13, 2012
    Date of Patent: November 15, 2016
    Assignee: GTAT Corporation
    Inventors: Dean C. Skelton, Brett C. Forlano
  • Polishing composition
    Patent number: 9493678
    Abstract: A polishing composition comprising abrasive particles, a compound having hexavalent molybdenum or pentavalent vanadium, an anionic additive, a halogen oxides compound or salts thereof, and a carrier solvent is provided herein. The polishing composition is suitable for chemical mechanical polishing process of SiGe, Si and SiO2 substrates. The compound having hexavalent molybdenum or pentavalent can effectively raise the removal rate for SiGe and Si substrates, and increase the polishing selectivity of SiGe and Si relative to SiO2, simultaneously.
    Type: Grant
    Filed: January 15, 2015
    Date of Patent: November 15, 2016
    Assignee: UWiZ Technology Co., Ltd.
    Inventors: Yun Lung Ho, Chun Chieh Lee, Song Yuan Chang, Ming Hui Lu, Ming Che Ho
  • Fabrication method of plate pattern
    Patent number: 9489099
    Abstract: Disclosed herein is a fabrication method of a plate pattern including preparing an object on which the plate pattern will be formed, disposing hybrid particles having a hybrid structure of organic and inorganic substances on one surface of the object into a single layer, etching at least the hybrid particles, forming the plate pattern on the surface of the object on which the hybrid particles are disposed, and removing the hybrid particles.
    Type: Grant
    Filed: April 28, 2015
    Date of Patent: November 8, 2016
    Assignee: LG Electronics Inc.
    Inventors: Hooyoung Song, Minwoo Lee
  • Method for structuring a layered structure from two semiconductor layers, and micromechanical component
    Patent number: 9490137
    Abstract: A method for structuring a layered structure, for example, of a micromechanical component, from two semiconductor layers between which an insulating and/or etch stop layer is situated includes forming a first etching mask on a first side of the first semiconductor layer, carrying out a first etching step, starting from a first outer side, for structuring the first semiconductor layer, forming a second etching mask on a second side of the second semiconductor layer, and carrying out a second etching step, starting from the second outer side, for structuring the second semiconductor layer. After carrying out the first etching step and prior to carrying out the second etching step, at least one etching protection material is deposited on at least one trench wall of at least one first trench, which is etched in the first etching step.
    Type: Grant
    Filed: February 6, 2015
    Date of Patent: November 8, 2016
    Assignee: ROBERT BOSCH GMBH
    Inventors: Simon Armbruster, Frank Fischer, Johannes Baader, Rainer Straub