Abstract: A disk drive is disclosed comprising a bias layer in a magnetoresistive (MR) head actuated over a disk having a plurality of data tracks, each data track comprising a plurality of sectors. A sync mark detector detects a sync mark pattern in a sector, wherein when the sync mark pattern is detected a sync mark detect signal and a polarity signal are generated. The polarity signal indicates when the polarity of the bias layer has deviated from a preferred polarity, wherein the polarity of the bias layer is realigned back toward the preferred polarity.

Abstract: An inner gap in between the first and the second magnetic films is embedded by an insulating film, on which the second magnetic film is formed. The coil film is embedded in the insulating film. An inductive type electromagnetic conversion element is covered with a protection film entirely. Provided that the minimum thickness on the second magnetic film of the protection film is “A” and the maximum thickness in the inner gap of the insulating film is “B”, the relation of “1≦(A/B)≦2.5” is satisfied.

Abstract: A method of replacement processing for secondary defects is provided that can maintain both the transfer rate and quality of write/read data at high levels. According to the method, a change-permitted range in which changes in the assignment of logical addresses is allowed is acquired, and when sectors having secondary defects due to write abnormalities are detected, replacement of sectors is carried out as long as changes in the assignment of logical addresses do not go beyond sectors in the change-permitted range by: omitting the secondary defect sectors by additionally registering the defective sectors in a slip replacement list, and shifting back the assignment of logical addresses as long as there are free sectors following the abnormal sectors.

Abstract: A first counter sequentially counts a plurality of numbers from respective sources requesting transfer of data. Each of the numbers represents an amount of isochronous data to transfer over the bus from the respective ones of the sources during a frame on a bus. A count value in a second counter is selectably incremented when the first counter is counting, to provide a remaining count value indicative a remaining amount of data to transfer during the frame. The remaining count value in the second counter is decremented for each isochronous transfer on the bus after the remaining amount of data to transfer has been determined from all sources requesting transfer of isochronous data during the frame. A third counter tracks the time remaining in the frame and compares the remaining count value to the time remaining in the frame to determine a priority mode on the bus.

Abstract: A method of determining a route to be tested in the testing of a load module which includes a multiplicity of routes (route patterns) from the start to the end of the program, each route pattern being composed of a multiplicity of route paths. The method comprises the steps of: (1) testing an untested route pattern and managing the current state of the testing of all the route patterns with the untested route pattern changed to a tested route pattern; (2) managing the current state of the testing of all the route paths with the route paths constituting the untested route pattern changed to tested route paths; and (3) determining an untested route pattern which is constituted by the largest number of untested route paths to be the route pattern to be tested next. These steps are repeated until there exists no untested route path in the load module test.

Abstract: To simplify the process relative to an instruction array including an instruction for a process with flag handling executed by a compiler when converting a high-level program into in a format executable by a program executing apparatus, a number of operating circuits, namely, an ALU circuit and a AND operation circuit, are provided to operate in parallel to handle different flags in a flag group based on the results of respective operations. A value comparison instruction and a bit test instruction are converted into common operation process instructions, and branch instructions, dependent on the result of the execution of the operation process instructions, are prepared so as to detect different flag patterns. The common use of an operation instruction for a number of flag-handling instructions simplifies a compiler judgement.

Abstract: A method and system for operating a computing system having multiple processing units. According to a new machine instruction, called the iota instruction, the computing system operates on a vector of mask bits to generate an iota vector having a sequence of values. In one form, each value of the iota vector is a sum of a series of the lower order mask bits up to and including the mask bit corresponding to the entry in the iota vector. In another form, each entry in the iota vector is a sum of a series of lower order mask bits but does not include the mask bit corresponding to the particular entry in the iota vector. In order to calculate the iota vector, the multiple processing units of the present invention communicate the mask bits to the other processing units. Advantages of the present invention include the vectorization of software loops having certain data hazards that prevented conventional compilers from vectorizing the software.

Abstract: A method and system for re-using special purpose registers as general purpose registers utilized a special variable type to indicate that a variable may safely be stored in a special purpose register. A loader program maintains the table indicating the availability of special purpose registers for variable storage and loads a variable of the special type to an available special purpose register.

Abstract: A method and apparatus for providing for serially transmitting partitioning information between system partitions, and between system partitions and the corresponding data processing resources. Serial transmission may allow the partitioning information to be transmitted using a single I/O ASIC pin, and a single PC board trace. In addition to reducing the required number of I/O ASIC pins and PC board traces, the present invention may increase the overall reliability of the partitioning mechanism.

Abstract: A program controller for use in a processor operating on pipe-line principles includes: a first memory section for outputting an instruction contained in a first program including a plurality of instructions; a second memory section for outputting an instruction contained in a second program including a plurality of instructions, the first program being different from the second program; a selection section for selecting either the instruction which is output from the first memory section or the instruction which is output from the second memory section; a determination section for determining whether or not the instruction selected by the selection section is an instruction for controlling the execution order of instructions; and a control section for, if the instruction selected by the selection section is determined as an instruction for controlling the execution order of instructions, controlling the selection section so as to switch from the selected instruction to the unselected instruction of either th

Abstract: In a superscalar processor, multiple instructions are executed in parallel to obtain multiple execution results, and the multiple execution results are stored in a working register file. Each execution result in the working register file has at least one status bit associated therewith which identifies the execution result as valid data. The multiple execution results contained in the working register data then retired by changing the status bits associated with each execution result to identify the execution result as final data. In this manner, the speculative data is retired as the final data without data movement of the speculative data, thus reducing a number of ports needed in the superscalar processor.

Abstract: An arbiter system for the instruction issue logic of a CPU has at least two encoder circuits that select instructions in an instruction queue for issue to first and second execution units, respectively, based upon the positions of the instructions within the queue and requests by the instructions for the first and/or second execution units. As a result, since the instruction can request different execution units, this system is compatible with architectures where the execution units may have different capabilities to execute different instructions, i.e., each integer execution unit may not be able to execute all of the instructions in the CPU's integer instruction set. According to the present invention, one of the encoder circuits is subordinate to the other circuit. The subordinate encoder circuit selects instructions from the instruction queue based not only on the positions of the instructions and their requests, but the instruction selection of the dominant encoder circuit.

Abstract: In one embodiment, a processor includes thread management logic including a thread predictor having state machines to indicate whether thread creation opportunities should be taken or not taken. The processor includes a predictor training mechanism to receive retired instructions and to identify potential threads from the retired instructions and to determine whether a potential thread of interest meets a test of thread goodness, and if the test is met, one of the state machines that is associated with the potential thread of interest is updated in a take direction, and if the test is not met, the state machine is updated in a not take direction. The thread management logic may control creation of an actual thread and may further include reset logic to control whether the actual thread is reset and wherein if the actual thread is reset, one of the state machines associated with the actual thread is updated in a not take direction.

Abstract: An embodiment of the invention is directed at a method for accessing a cache by detecting a branch instruction having an address and containing a first set of bits representing a displacement value, and generating a modified instruction containing a second set of bits representing a combination based on the first set of bits and the address.

Abstract: A multiple counter-rotating ring computer network system having a permission control scheme for client isolation. The peripheral channel allows two rings to be folded into one longer ring so that faulty nodes can be effectively removed from the network. Or, any of the rings can be masked so that they are unoperational. The network system also allows several client isolation states ranging from complete isolation to master access. These types of isolation allow faulty client devices to be tested while maintaining a high-level of network security by configuring the client to an appropriate isolation state.

Abstract: An apparatus and method are provided for executing a forward branch in a microprocessor. The apparatus has translation logic and instruction fetch logic. The translation logic utilizes a branch predictor to determine if a conditional branch should be taken or not. If the branch is predicted taken, then a branch accelerator in the instruction fetch logic determines if a branch target instruction has already been stored for translation in an instruction buffer by summing the length of the conditional branch instruction to a displacement provided by the conditional branch instruction. If the branch target instruction is already within the instruction buffer, contents of the instruction buffer are simply shifted by the number of bytes indicated by the sum to move the branch target instruction to the front of the buffer.

Abstract: The invention provides techniques for reducing the port pressure of a clustered processor. In an illustrative embodiment, the processor includes multiple clusters of execution units, with each of the clusters having a portion of a register file and a portion of a predicate file associated therewith, such that a given cluster is permitted to write to and read from its associated portions of the register and predicate files. A replication technique in accordance with the invention reduces port pressure by replicating, e.g., a register lock file and a predicate lock file of the processor for each of the clusters. The replicated files vary depending upon whether the technique is implemented with a write-only interconnection or a read-only interconnection.

Abstract: A data processing system contains a processor supporting instructions and operands utilizing a Narrow word size. The processor communicates over a bus utilizing a Wide word size with the remainder of the data processing system consisting of industry standard memory and peripheral devices. Narrow word sized instructions are stored on Wide word-sized storage devices. The translation between Narrow and Wide word sizes can be either at a byte/Unicode level, or at a word level.

Abstract: An electronic circuit package having a wiring substrate, at least two semiconductor chips and a bus line. All the semiconductor chips to be connected by means of the bus line are bare chip packaged on a wiring substrate, and the semiconductor chips and the wiring substrate are connected by wiring bonding between wire bonding pads formed on the semiconductor chips and the wiring substrate. The wiring substrate may be a multilayered substrate. Preferably, there is an insulating layer partially formed on the surface of the multilayer wiring substrate and a die bonding ground formed on the surface of the insulating layer, in order to use a portion of the multilayer wiring substrate under the die bonding ground as a wiring or a via hole region, and at least one of the semiconductor chips is formed on the die bonding ground.

Abstract: An inherently serial program is processed in parallel, thus leading to higher processing speeds, while maintaining a close approximation to the specific result obtained through a serial running of the program. This goal has been attained based on the fact that the desired degree of closeness between a parallel result and the serial result depends on the particular inherently serial program being run and the type of analysis being performed. That is, some inherently serial processes require a “fine-tuned” result while for others a “coarser” result is acceptable. The frequency at which the parallel branches consolidate their respective results is changed accordingly to alter the degree of closeness between the parallel processed result and the serially processed result.