Abstract: A packed data structure processor (25) is disclosed. The packed data structure processor (25) includes a register file (24) of multiple registers (REG0 through REG31), each of which is connected to an input of each of a plurality of operand multiplexers (26). Each operand multiplexer (26) is associated with a shift/mask circuit (28), which permits the selection of a particular portion (e.g., BYIE, WORD, DWORD) of the contents of a selected register file, for use as an operand. An arithmetic logic unit (ALU) (30) performs data processing operations upon the operands, and presents results on writeback bus (WBBUS), to external memory (18) over a memory interface (37), or to a register file (42) associated with other circuitry (44) over a coprocessor interface (41). A destination selector (40) is capable of writing to only a selected portion of a selected register, thus permitting a packed data structure to be present within the register file (24).

Abstract: A method and circuit is provided for preloading a branch prediction unit within a microprocessor. In one embodiment of the method, a branch history storage device such as branch history shift register is written with a predetermined multibit predicter in response to the microprocessor receiving and executing a special write branch history storage device instruction for writing the predetermined multibit predicter into the branch history storage device. The branch history storage device is contained within a prediction circuit of the microprocessor, and generally the contents of the branch history storage device is used in the process of predicting the results of executing conditional branch instructions prior to their execution.

Abstract: A massively-parallel computer includes a plurality of processing nodes and at least one control node interconnected by a network. The network faciliates the transfer of data among the processing nodes and of commands from the control node to the processing nodes. Each processing node includes an interface for transmitting data over, and receiving data and commands from, the network, at least one memory module for storing data, a node processor and an auxiliary processor. The node processor receives commands received by the interface and processes data in response thereto, in the process generating memory access requests for facilitating the retrieval of data from or storage of data in the memory module. The node processor further controlling the transfer of data over the network by the interface. The auxiliary processor is connected to the memory module and the node processor.

Abstract: A processor including at least one execution unit generating out-of-order results and out-of-order condition codes. Precise architectural state of the processor is maintained by providing a results buffer having a number of slots and providing a condition code buffer having the same number of slots as the results buffer, each slot in the condition code buffer in one-to-one correspondence with a slot in the results buffer. Each live instruction in the processor is assigned a slot in the results buffer and the condition code buffer. Each speculative result produced by the execution units is stored in the assigned slot in the results buffer. When an instruction is retired, the results for that instruction are transferred to an architectural result register and any condition codes generated by that instruction are transferred to an architectural condition code register.

Abstract: A data processor including: a CPU (1) for performing a wait operation upon input of a wait signal (10) to its wait terminal (9); a wait/wait cancel instruction setting register (11) to which the CPU (1) sets a wait instruction and a wait cancel instruction; and a wait controller (12) for outputting a wait signal to the wait terminal (9) of the CPU (1) in accordance with the setting of the register (11), wherein the inventive data processor allows a wait state to be set and canceled as programmed independently of address space constraints.

Abstract: A processor employs ordering dependencies for load instruction operations upon store address instruction operations. The processor divides store operations into store address instruction operations and store data instruction operations. The store address instruction operations generate the address of the store, and the store data instruction operations route the corresponding data to the load/store unit. The processor maintains a store address dependency vector indicating each of the outstanding store addresses and records ordering dependencies upon the store address instruction operations for each load instruction operation. Accordingly, the load instruction operation is not scheduled until each prior store address instruction operation has been scheduled. Store addresses are available for dependency checking against the load address upon execution of the load instruction operation. If a memory dependency exists, it may be detected upon execution of the load instruction operation.

Abstract: The present disclosure discloses a method for creating and using a dynamic universal resource locator to link an internet end user to a host selected from two or more hosts on the internet. The method comprises the steps of: (a) obtaining information related to either or both of the end user and/or the two or more hosts; (b) selecting, based upon the obtained information, one of the two or more hosts; and (c) generating a link to the selected host. Also disclosed is a method for connecting a user to a dial-up host having an internet domain name and a temporary internet address.

Abstract: An electronic circuit package having a wiring substrate, at least two semiconductor chips and a bus line. All the semiconductor chips to be connected by means of the bus line are bare chip packaged on a wiring substrate, and the semiconductor chips and the wiring substrate are connected by wiring bonding between wire bonding pads formed on the semiconductor chips and the wiring substrate. The wiring substrate may be a multilayered substrate. Preferably, there is an insulating layer partially formed on the surface of the multilayer wiring substrate and a die bonding ground formed on the surface of the insulating layer, in order to use a portion of the multilayer wiring substrate under the die bonding ground as a wiring or a via hole region, and at least one of the semiconductor chips is formed on the die bonding ground.

Abstract: Dynamically typed registers in a processor are provided by associating a type specifier with a register specifier for each register in the processor, storing the register specifiers and associated type specifiers in a register type table. The type specifier associated with an operand register of an instruction is employed to dispatch the instruction to an appropriate execution unit within the processor. The results of the instruction are stored in a register having an associated type specifier matching the execution unit type. Register specifiers are dynamically allocated to particular execution units within the processor by altering the type specifier associated with the register specifiers. Register values may be either discarded or converted when the register specifier type is altered. A general instruction allows conversion of the value from one type to another without storing the converted value in memory.

Abstract: Disclosed is a method and apparatus for accessing data in a computer system after a failed data operation in which I/O process state information is unknown. The failed data operation may cause data inconsistency among multiple devices associated with a shadow set for storing data. The disclosed system includes techniques for allowing continued data accesses while simultaneously re-establishing data consistency among members of the shadow set.

Abstract: A processor architecture scheme which allows for encoding of multiple addressing modes through use of virtual register addresses in order to maximize number of directly addressable registers in the processor architecture scheme. A set of virtual address register locations associated with an indirect addressing pointer is reserved in memory. The number of virtual register address locations reserved is equal to a number of indirect addressing modes associated with the indirect addressing pointer. Each of the virtual register address locations initiates an indirect addressing mode to be used with the associated indirect addressing pointer when accessed.

Abstract: A process stop method and apparatus applicable to a distributed memory multi-processor system allows an efficient stop processing for the entry of a checkpoint during parallel processing where data are communicated between different nodes. The system comprises a plurality of nodes interconnected through a network, each of which is provided with a thread for parallel processing. Each of the nodes has a management process to manage its own thread engaged in parallel processing. When a request for a checkpoint is dispatched as an external command, the management process of a node whose node number is the smallest requests a stop from the thread of the same node. After confirming that the thread in question has stopped, the management process delivers a stop request to the management process of a node whose node number is the next smallest.

Abstract: A method of debugging and a method of monitoring an analysis instrument are provided. A microcomputer of the analysis instrument is provided with a debugging personal computer connected thereto via remote communication means. The analysis instrument has detecting means for checking operation status installed therein. An operator debugs contents stored in the analysis instrument via the communication means after checking as to whether trouble exists in each device according to testing information provided by the detecting means.

Abstract: An apparatus for processing data has a Single-Instruction-Multiple-Data (SIMD) architecture, and a number of features that improve performance and programmability. The apparatus includes a rectangular array of processing elements and a controller. The apparatus offers a number of techniques for shifting image data within the array. A first technique, the ROLL option, simultaneously shifts image planes in opposite directions within the array. A second technique, the gated shift option, makes a normal shift of an image plane to neighboring PEs conditional, for each PE, upon a value stored in a pattern register of each PE. A third technique, the carry propagate option, combines the computations from multiple PEs in order to complete an n-bit operation in fewer than n clocks by forming “supercells” within the array. The apparatus also includes a multi-bit X Pattern register and a multi-bit Y Pattern register.

Abstract: In the CIS installation area of a PC card, the A region contains the basic attribute information of the card, the B region contains data of CIS1 for a modem, and the C region contains CIS2 for an ATA memory. The PC card is provided with a selection signal input means which selectively designates the CIS. A selection signal discriminator receives a signal from the selection signal input means and determines the selective designation of the CIS. When CIS1 and CIS2 are selectively designated together, a CIS switch setting element sets the start of the CIS read-in by a personal computer to the leading address of CIS1, and when CIS2 only is selectively designated, it switchably sets the start of the CIS read-in by the personal computer to the leading address of CIS2.

Abstract: An apparatus and method for calculating a square root of an operand in a microprocessor are provided. The microprocessor has a plurality of square root instructions, each of which specifies a square root calculation precision. The apparatus includes translation logic and execution logic. The translation logic decodes the square root macro instruction into a plurality of prescribed-precision machine instructions according to the square root calculation precision specified by the plurality of square root instructions. The execution logic, coupled to the translation logic, receives the plurality of prescribed-precision machine instructions and calculates the square root of the operand according to the specified square root calculation precision. At least one of the plurality of square root instructions specifies the square root calculation precision such that less significant bits are calculated in the square root than are provided in the operand.

Abstract: A processor provides trace capability. Trace information can be provided over a communication port that is operable both as a trace port and as a parallel debug port. The trace port provides trace information indicating instruction execution flow in the processor core. The operation of the communication port as a trace port and as a parallel debug port is mutually exclusive. The parallel debug port provides for transmission of debug information between a debug host controller and the processor. The parallel debug port and the trace port physically share pins. Bus request and grant signals are provided between the parallel debug port and a debug host controller to ensure that collisions do not occur between use by the trace port and the debug host controller. A separate serial debug port is also provided which can be used to enable the parallel debug port.

Abstract: A data processing unit is described which comprises a central processing unit, a bus coupled with the central processing unit to access a device via address and data lines coupled with the bus. A debug unit is coupled to the bus, a protection unit is coupled with the bus and with the debug unit for protecting access on the bus. The protection unit is programmable to operate in a protecting mode in which the bus can be protected and in a debug mode in which a signal is sent to the debug unit, whereupon the debug unit generates a debug signal.

Abstract: Systems, apparatus, and methods are disclosed for generating pairs of conditional instructions corresponding to special predicate sequences from single instructions having a predicate. These pairs of conditional instructions update a destination register regardless of the truth or falsity of the predicate. The destination register is renamed to a new physical location. In this manner, register renaming can be used with predicate sequences to gain performance efficiencies and to overcome limitations of the prior attempted approaches.

Abstract: An apparatus including a banked instruction cache and a branch prediction unit is provided. The banked instruction cache allows multiple instruction fetch addresses (comprising consecutive instruction blocks from the predicted instruction stream being executed by the microprocessor) to be fetched concurrently. The instruction cache provides an instruction block corresponding to one of the multiple fetch addresses to the instruction processing pipeline of the microprocessor during each consecutive clock cycle, while additional instruction fetch addresses from the predicted instruction stream are fetched. Preferably, the instruction cache includes at least a number of banks equal to the number of clock cycles consumed by an instruction cache access. In this manner, instructions may be provided during each consecutive clock cycle even though instruction cache access time is greater than the clock cycle time of the microprocessor.