Abstract: A network management system includes a user interface, a virtual network and a device communication manager. The virtual network includes models which represent network entities and model relations which represent relations between network entities. Each model includes network data relating to a corresponding network entity and one or more inference handlers for processing the network data to provide user information. The system can poll or communicate with certain network entities and can infer the status of network connectors and other network entities for which polling is impossible or impractical. The system performs a fault isolation technique wherein the fault status of a network device is suppressed when it is determined that the device is not defective. User displays include hierarchical location views and topological views of the network configuration.

Abstract: To provide a signal processor for performing processing in fewer cycles by selecting one of the two different operations in accordance with a flag signal and performing the selected operation without the use of a conditional branch instruction, the signal processor is provided with an instruction decoder, a control selecting circuit, a selecting circuit and an arithmetic unit. The instruction decoder decodes an instruction to output two control signals. The control selecting circuit is connected to the instruction decoder and selects one of the control signals in accordance with a flag signal stored in a flag holding circuit to output the selected signal. The selecting circuit selects one of a plurality of input data in accordance with the control signal outputted by the control selecting circuit and outputs the selected data. The arithmetic unit performs an operation on the data outputted by the selecting circuit.

Abstract: A system and method are described for maintaining synchronization of information propagating through multiple front-end pipelines operating in parallel. In general, these multiple front-end pipelines become asynchronous in response to a stall condition and re-establish synchronization by flushing both front-end pipelines as well as by selectively releasing these front-end pipelines from their stall condition at different periods of time.

Abstract: The method for electronically conveying large blocks of data between geographically-remote locations by uploading the sender's data to the local hub site of a service provider's network, earmarking that data with an electronic invoice, transmitting that data via the service provider's high speed network to a secondary hub site that is local to the recipient's geographic location, and downloading the data from the second hub site to the recipient's network. Duplicate archival versions of the transmitted data may be maintained at two geographically-distinct locations, such as the service provider's primary and secondary network hub sites. The total number of network connections may be reduced with a minimum number of alternative connections maintained to ensure data delivery in the event of a network connection failure. Value-added services may be performed on the data either prior or subsequent to its transmission between the primary and secondary hub sites.

Abstract: In the system bus controller of a multi-processor system, apparatus is provided for selecting one of the processors to handle an interrupt. A mask is provided for each respective task being executed on each one of the processors. Each mask includes a speculation bit identifying whether the task is speculative. Each mask includes a plurality of class enable bits identifying whether the task can be interrupted by a respective class of interrupts associated with each of the plurality of class enable bits. Control lines in the system bus receive an interrupt having a received interrupt class. A subset of the processors is identified; processors in the subset can be interrupted by the received interrupt based on the received interrupt class and the respective speculation bit and class enable bits assigned to the task being executed on each respective processor. A Boolean AND operation is performed on the mask associated with the respective task executing on each processor.

Abstract: A communications system utilizes an embedded Digital Signal Processor (DSP), a DSP interface and memory architecture, a micro-controller interface, a DSP operating system (OS), a data flow model, and an interface for hardware blocks. The design allows software to control much of the configuration of the architecture while using hardware to provide efficient data flow, signal processing, and memory access. In devices with embedded DSPs, memory access is often the bottleneck and is tightly coupled to the efficiency of the design. The platform architecture involves a method that allows the sharing of the DSP memory with other custom hardware blocks or the micro-controller. The DSP can operate at full millions-of-instructions-per-second (MIPS) while another function is transferring data to and from memory. This allows for an efficient use of the memory and for a partitioning of the DSP tasks between software and hardware.

Abstract: A bus switch providing versatile data path routing between a first group of busses associated with a disk array controller and a second group of busses associated with the individual disk drives within the disk array. The bus switch comprises a plurality of bus multiplexers, equal in number to the number of drive busses. Each bus multiplexer includes a plurality of inputs, each input being connected to a corresponding one of the controller busses. The multiplexers are responsive to select and enable signals to connect selected controller busses to selected drive busses. The bus switch additionally includes a plurality of bus multiplexers for directing data from the drive busses to the controller busses. A parity generator comprising an exclusive-OR circuit is integrated with the bus switch. The output of the parity generator is also provided to each of the multiplexers and can be directed thereby to any of the controller or drive busses.

Abstract: To improve the efficiency of delayed transactions in bus-to-bus bridge systems which include at least one interface to a PCI bus, a bridge system is disclosed including at least a primary interface and an interface to a secondary subsystem for interconnecting a primary PCI bus system and the secondary subsystem. The system comprises a delayed transaction mechanism for enabling a transaction source attached to the primary PCI bus system to effect delayed transactions with a target in the secondary subsystem. This system has a programmable delay transaction timer which provides a degree of flexibility in the configuration of PCI systems. This flexibility can be exploited to provide considerable efficiency gains, albeit at the expense of some deviation of the strict requirements of the PCI Specification.

Abstract: Method and apparatus for automatically populating a network simulation tool database with network topology and/or traffic information. A topology extraction tool is provided for reading the topology and traffic information in a network management system database, and translating this information into a matching data format required by the simulation tool database before writing the information to the simulation tool database. This automatic method avoids the time-consuming and error-prone prior art manual method of constructing a network model.

Abstract: A translation gateway for a distributed computing environment including a source computer system and a target computer system, each of which has at least one client, one server and a distributed file system, and wherein the server associated with the source computer system preferably runs on a client of the target computer system. A method for providing authenticated access to files stored in the target distributed file system in response to file requests originating from clients associated with the source distributed file system begins by mapping credentials associated with incoming client requests from the source distributed file system into enhanced credentials containing authentication information associated with an authentication model of the target distributed file system. At least one enhanced credential is then augmented with one or more attributes whose values may be extracted and used in the processing of the filesystem request by the target file system.

Abstract: A high availability on-line transaction processing (OLTP) system utilizes both hardware and software. Geographically separated primary (live) and backup (shadow) communications servers link live and shadow OLTP systems to geographically separated live and shadow Wide Area Networks and remote client computers. The remote client computers communicate with the live and shadow OLTP systems through their respective live and shadow WANs and communications servers. The live OLTP system sends "keep-alive" messages to the shadow system via the dedicated circuits on a frequent basis. If the shadow OLTP system does not receive a keep-alive message from the live system within a designated time interval, it sends "probe messages" to the live communications servers and live OLTP system, via the shadow WAN, client computers and live WAN to determine their status.

Abstract: A transmit scheduler and method of operation are provided for an asynchronous transfer mode network. The transmit scheduler is operable to write data to and read data from a scheduler table and a virtual channel identifier ("VCI") table in order to schedule cells for virtual channels. The transmit scheduler calculates a location in the scheduler table in which to schedule a cell for a current virtual channel and determines whether a cell for a prior virtual channel is scheduled in the calculated location in the scheduler table. The transmit scheduler then schedules the cell for the current virtual channel at the calculated location in the scheduler table. If a cell for a prior virtual channel was scheduled in the calculated location in the scheduler table, the transmit scheduler writes a pointer into a next pointer field of a record for the current virtual channel in the VCI table, where the pointer provides a link to a record for the prior virtual channel in the VCI table.

Abstract: A processor that executes coded instructions using an instruction scheduling unit receiving the coded instructions and issuing an instruction for execution. A replay signaling device generates a signal indicating when the instruction failed to execute properly within a predetermined time. A replay device within the instruction scheduling unit responsive to the signaling device then reissues the instruction for execution.

Abstract: A processor to coprocessor interface supporting multiple coprocessors utilizes compiler generatable software type function call and return, instruction execute, and variable load and store interface instructions. Data is moved between the processor and coprocessor on a bidirectional shared bus either implicitly through register snooping and broadcast, or explicitly through function call and return and variable load and store interface instructions. The load and store interface instructions allow selective memory address preincrementation. The bi-directional bus is potentially driven both ways on each clock cycle. The interface separates interface instruction decode and execution. Pipelined operation is provided by indicating decoded instruction discard by negating a decode signal before an execute signal is asserted.

Abstract: A data processor employs simple hardware to improve the efficiency of supplying instructions. The data processor has a cache memory to store blocks of instructions. Each block is divided into at least two sub-blocks. The data processor is capable of simultaneously reading sub-blocks belonging to different blocks and rearranging the read sub-blocks in order.

Abstract: A processor processes a plurality of instructions according to a disclosed method. First, the method receives (32) an instruction from the plurality of instructions. Second, the method determines (34) whether the received instruction is preceded by an instruction path leading code. Third, the method passes (36 or 38) the received instruction along at least one instruction path in a plurality of instruction paths. Fourth, in response to determining that the received instruction is preceded by an instruction path leading code, the method executes a machine word corresponding to the received instruction and selected from one of the plurality of instruction paths. Specifically, the selected instruction path is selected in response to the instruction path leading code.

Abstract: In a superscalar processor for fetching a prescribed peak number of instructions in parallel in each period until such instructions are fetched to a predetermined peak number, such as ten, an instruction parallel issue and execution administrating device comprises a forward map buffer for a forward map indicative of a result of each instruction for use as an operand by which one of other instructions of the predetermined peak number. The forward map is developed before the result is actually produced and is used, after the actual production, to indicate which one of such results should be used as the operand by the above-mentiond one of the other instructions.

Abstract: A system and method for providing a microprocessor with a software accessible serial number. A plurality of programmable fuses on the processor are encoded with a value representative of a serial number. Circuitry is provided on the processor for transferring the value encoded on the programmable fuses to a machine specific or general purpose register or storage device. The machine specific or general purpose register or storage unit is software accessible.

Abstract: A buffer circuit of a decentralized peripheral module. The buffer circuit has three input and three output signal storage areas, which can be selectively connected to a bus interface or a module interface via a selection circuit. Thus the process signal transfer from an intelligent unit arranged on the module to a unit of a higher level than the module and vice-versa can be completely separated.

Abstract: A distributed computer system is disclosed which comprises a source of a continuous data stream repetitively including data representing a distributed computing application and a client computer, receiving the data stream, for extracting the distributed computing application representative data from the data stream, and executing the extracted distributed computing application.