Abstract: An apparatus for and method of loading the addressing environment of a large scale multiprogrammed instruction processor. The addressing environment is normally loaded upon initiation of an application program. Providing a separate addressing environment for each application program permits the software to be developed using virtual addressing. The addressing environment is loaded to permit the instruction processor to convert the virtual addresses to absolute addresses. The addressing environment is specified by a stack of base registers. These are loaded sequentially from a data store containing the virtual address of the initial location of each data bank to be accessed. The virtual addresses are converted to absolute addresses for loading into the base registers. During the loading process, each virtual address is evaluated to determine if it defines a valid data bank. If it does, the corresponding base register is loaded.

Abstract: By using a shared register directory having a bit array corresponding one to one to the processor for each shared register, a shared register control portion of a shared register control system in a multiprocessor system monitors to which processor each of the registers shared between processors is currently allocated or if it is not allocated to any of the processors at all (unoccupied condition), and allocates any arbitrary shared register in response to the request from each processor while allowing access to the allocated share register. A task on the processor, which had been initially using the shared register, can be switched even if another task using the same register is being executed on any other processor, and the throughput of the multiprocessor system using the shared register can be increased.

Abstract: A multiprocessor data processing system (10), and a method of operating same, so as to provide efficient bandwidth utilization of shared system resources (24, 26). The system includes a plurality of processor nodes, each of which includes a data processor (22a, 28a). A first step of a method buffers data written by a data processor to a first bus (23a), prior to the data being transmitted to a second bus (32). Also buffered are byte enable (BE) signals generated by the data processor in conjunction with the data written by the data processor. A next step performs a main memory (26) write operation by transmitting the buffered data to the second bus; responsive to the stored BE signals, also transmitting a control signal for indicating if a memory write is to be accomplished as a read-modify-write (RMW) type of memory operation; and transmitting the stored BE signals to the second bus.