Abstract: A routable operand and selectable operation processor multimedia extension unit is employed to motion compensate MPEG video using improved vector processing. A vector processing unit executes an add and divide instruction that adds two vector registers and divides the result in a single instruction. This is implemented through loading a first vector register with a first plurality of elements from a source block. A second vector register is then loaded with a second plurality of elements that are adjacent to the first plurality of elements. The add and divide instruction is then executed on the first and second vector registers, yielding an interpolated source element that is stored in a resultant vector register.

Abstract: A one-chip microprocessor, in which a built-in cache memory unit 20 has parities, and a cache parity generating & checking unit 21 checks parity of data read from the built-in cache memory unit 20, and when parity error is detected, outputs an internal cache parity error signal 50 to an instruction execution unit 23. By this, the instruction execution unit 23 suspends instruction execution and outputs a processor error signal 37. Accordingly, by checking parity errors of data of built-in memory and inputted address/data, instruction execution are immediately suspended to limit malfunction at least, thereby improving reliability. And by storing kinds of bus operation and errors in a register at the time of error generation, restoring possibility of system level is improved.

Abstract: A microprocessor having a replay architecture with an execution core for performing data speculation in executing an instruction, a delay unit for making a copy of the instruction and holding the copy for as long as the instruction takes to execute, and a checker for determining whether the data speculation was bogus. If the data speculation was bogus, the delay unit and its buffer send the copy of the instruction back to the execution core for re-execution. A multiplexor coupled to the input of the execution core selects for execution among original instructions from the instruction cache, replay instructions from the delay unit, and manufactured instructions from various other units such as the TLB or tag units, according to a priority scheme.

Abstract: An improved apparatus for processing a repeatedly performed arithmetic operation for a digital signal processor and a method thereof which are capable of pushing and popping values related to a repeat block to a register having a stack structure by providing a stack structure for processing a repeat block, this enabling a nested loop.

Abstract: An external bus I/F section has a function in which, when a bus access is requested by an instruction execution section, high-order several bits of a logical address generated by a CPU are outputted from an output terminal to the outside of a chip, as a space identifier for indicating which of an integrated ROM space, an integrated RAM space, and the external space is accessed by a currently executed program. A part of an address generated by the CPU is used so that the space which is accessed by the currently executed program is known from the outside in real time without requiring an external hardware.

Abstract: A computer system with a plurality of devices compatible with the Fibre Channel Protocol, which computer system is provided with the capability to dynamically alter the configuration of the plurality of devices without a system reset, or without additional software overhead. This capability is realized by providing unique mapping relationships between low-level Fibre Channel information structures related to the devices and upper-level link elements compatible with an Operating System associated with the computer system.

Abstract: A system and method for minimizing space requirements and increasing speed in a geometry accelerator for a computer graphics system by enabling efficient multiway logic branching functionality. Architecturally, the system is implemented as follows. A plurality of processing elements (stack) are disposed in the geometry accelerator along with a plurality of control units that are implemented in a read-only memory (ROM) via microcode. Each of the control units is configured to drive a processing element in order to modify image data. A next address field is associated with each of the microcode instructions and defines a location in the ROM of a next instruction to be executed. A branch logic unit including a plurality of control unit logic elements. The plurality of control unit logic elements correspond respectively with the control units and are configured to assist with internal instruction branching within their respective control units.

Abstract: A computer system having a facility for concurrently sharing objects or resources is described. The system includes a publish-and-subscribe facility or "Object Exchange," for facilitating sharing among workgroups. When a data object is "published" by a user ("publisher"), the object is sent from that user's computer to other computer users specified by the publisher. Those interested in the published data object (published pages) may elect to receive or "subscribe" to that data. From that point on, the publisher can choose to update the data, such as whenever the published version changes. The "subscribers" of the published pages automatically get updates. Subscribers of a spreadsheet notebook, for instance, would automatically receive pages as they are published. The Object Manager effects actions by posting messages or "forms" to either the local Object Exchange (assuming one is the publisher) or the Object Exchange of others (subscribers).

Abstract: A verifier is provided for assessing unique characteristics exhibits by a user over a period of time. The unique characteristics are captured through various interactions with the user over time using a habit capture system which models the user's characteristics when he or she uses a keyboard, a mouse or a digitizer, among others. When the system is first used, the user is prompted to answer various questions, some of which inquire into personal information. As the user responds, information representative of the user is captured, including keyboard typing patterns, mouse click patterns, misspelling patterns, among others. Data captured by the habit capture system is provided to a verifier which samples the user's characteristics and compares the characteristics of the current user with that stored in a database.

Abstract: A network operating information setting system includes a design device, an automatic setting device and a network device. The design device has the function of producing a command chain of information which an operator designs using a GUI (Graphical User Interface) in order to store the command chain thus produced in a storage medium such as a floppy disk. In addition, the design device also has the function of reading out data from the storage medium in order to display the data thus read out. The automatic setting device has the function of reading out the command chain from the storage medium in order to transmit the command chain thus read out to the network device through a data transmission line. In this connection, an inverse command chain may be produced which is used to restore the network operating information to the original information in the network device.

Abstract: A core logic chip set is provided in a computer system to provide a bridge between host and memory buses and an accelerated graphics port ("AGP") bus adapted for operation of two AGP devices, or one AGP device and one peripheral component interconnect ("PCI") device. A common AGP bus having provisions for the PCI and AGP interface signals is connected to the core logic chip set and the AGP and/or PCI device(s). The core logic chip set has an AGP/PCI arbiter having Request ("REQ") and Grant ("GNT") signal lines for each AGP and/or PCI device connected to the AGP bus. Another embodiment has a plurality of AGP buses for a plurality of AGP devices. This allows concurrent operation for AGP devices connected to different AGP buses. Two of the AGP buses may be combined to connect to one 64 bit PCI device.

Abstract: A superscalar microprocessor predecodes instruction data to identify the boundaries of instructions and the type of instruction. In one embodiment, to expedite the dispatch of instructions, the first microcode instruction of the cache line is identified during predecode and stored as a microcode pointer. When the cache line is scanned for dispatch, the microcode pointer is used to identify the first microcode instruction which is conveyed to the MROM unit. In another embodiment, the first scanned instruction is predicted to be a microcode instruction and is dispatched to the MROM unit. A microcode scan circuit uses the microcode pointer and the functional bits of the predecode data to multiplex instruction specific bytes of the first microcode instruction to the MROM unit.

Abstract: An instruction executing section supplies an instruction of a certain context to a pipeline and executes the context. When a vacancy of the pipeline is judged, the instruction executing section switches the context to another context which is being executed, thereby simultaneously executing a plurality of contexts. An ID setting section sets a peculiar context ID to each of the plurality of contexts which are simultaneously executed by the instruction executing section. A register renaming section executes a multi-renaming such that a register name which is used when the plurality of contexts are simultaneously executed by the instruction executing section is renamed to a register name CIDi-Rj obtained by adding a designation register name Rj (j=1, 2, 3, . . . , m) of an execution instruction to CIDi as a context ID which was set by an ID setting section and whose context is being executed and the physical register is allocated.

Abstract: A client computer system and associated method in a computer network over which are provided programs with methods. The client computer is capable of executing the programs with reduced run-time memory space requirements. Specifically, a network communications interface receives the methods of the programs and a network communications manager loads uncompressed in available space in the run-time memory the methods when they are received. An execution controller controls execution of the programs so that the methods are invoked and not invoked at various times during execution of the programs. A compressor compresses in the memory compressible ones of the uncompressed methods that are not invoked so that space is made available in the run-time memory. The compressor also decompresses in available space in the run-time memory decompressible ones of the methods so that they may be invoked.

Abstract: A configuration manager for configuring a network device remotely coupled thereto and an associated computer-implemented method for configuring the network device. The configuration manager includes a configuration script stored in a memory subsystem of a computer system and first and second software modules respectively executable by a processor subsystem of the computer system. The configuration script contains a series of executable instructions for constructing a configuration file and a bootptab file for a first specified type of network device. By executing the instructions contained in the configuration script, the first software module may construct a configuration file suitable for upload to a network device and a bootptab file suitable for identifying the network device.

Abstract: A data management system and a method of distributing information units within the system is provided. The system comprises a host processor and plurality of controllers connected to the host processors in a local area network configuration. Each of the plurality of controllers provides access to any user, and each is provided with data storage capacity in the form of local storage in which information units are stored. The host processor manages all information units and their movement within the system. The host processor maintains a directory of all information units stored in the controllers in the system, allowing it to route a particular information unit to a controller for delivery to one or more users at a predetermined time.

Abstract: A method for controlling a document creation apparatus creates documents in accordance with an open document architecture. The documents contain one or more pages, with each of the pages containing one or more layout components. The method of the invention comprises the steps of selecting one page from a document being created; selecting a layout component from that one page in the document, the selected layout component forming a hierarchical component for the one page of the document; examining whether or not the selected layout component has a relationship with respect to another layout component; and setting a predetermined character string indicative of the relationship such that the predetermined character string is set in an attribute of the selected layout component in a form that may be read by a user, when the relationship exists.

Abstract: In a computer equipped with a mask register in which is stored mask data indicating, for each array element, whether or not a statement such as an IF statement or an ELSE statement should be applied, the computer having a vector processor executing vector operation processing according to the mask data stored in the mask register, a first executing unit acquires first and second memory areas in which the mask data is saved in a stack formation. A second executing unit generates, when an IF statement appears in execution of a program, mask data indicating truth/falsity of a conditional expression of the IF statement, and saves the mask data indicating the truth/falsity of the conditional expression in the first memory area. A third executing unit reads latest mask data saved in the second memory area in synchronism with a process of the second executing unit.

Abstract: A bus for transferring data is disclosed wherein the bus supports asynchronous, synchronous and high speed synchronous data transfers of varying size. The bus includes a master component for controlling data transfers with one or more slave components attached to the bus. Each data transfer is either received or supplied by the master via a set of data lines common to each slave component. Further, there are different control lines between the master and the slave components depending on the protocol(s) supported by each of the slaves. In particular, a slave supporting a high speed synchronous protocol is connected to the master by four control lines dedicated to providing control signals for implementing a high speed synchronous protocol handshake. Further, a fifth such control line is used to select a slave for a high speed synchronous data transfer when there is a plurality of high speed synchronous slaves.

Abstract: A method and apparatus for simulating the effect of non-homogeneous fog in an image displayed on a screen. The image is intended to represent the appearance of a model defined in a database in world space coordinates from an eyepoint position in world space, the model being defined in terms of individual features each having predetermined attributes defining the position and visible characteristics of the feature. Image data is derived from the model for each of an array of sampling points distributed across screen space. A non-homogeneous fog structure is defined in world space coordinates as a series of parallel strata of predetermined extinction coefficients. The positions of the eyepoint and a feature to be displayed relative to the fog structure are determined. The distance from the feature to the eyepoint is calculated.