Patents Examined by Eddie C. Lee
  • Patent number: 7173322
    Abstract: The present invention provides a COF flexible printed wiring board whose insulating layer is not melt-adhered to a heating tool, to thereby enhance reliability and productivity of a semiconductor chip mounting line, and also provides a method of producing the COF flexible printed wiring board. The COF flexible printed wiring board contains an insulating layer, a wiring pattern, on which a semiconductor chip being mounted, formed of a conductor layer provided on at least one side of the insulating layer and a releasing layer, wherein the releasing layer is formed from a releasing agent containing at least one species selected from a silane compound and silica sol and is provided on a surface of the insulating layer, which is opposite to the mounting side of the semiconductor chip.
    Type: Grant
    Filed: March 12, 2003
    Date of Patent: February 6, 2007
    Assignee: Mitsui Mining & Smelting Co., Ltd.
    Inventors: Ken Sakata, Katsuhiko Hayashi
  • Patent number: 7170187
    Abstract: Disclosed is a laminated (or non-laminated) conductive interconnection for joining an integrated circuit device to a device carrier, where the conductive interconnection comprises alternating metal layers and polymer layers. In addition, the polymer can include dendrites, metal projections from the carrier or device, and/or micelle brushes on the outer portion of the polymer. The polymer layers include metal particles and the alternating metal layers and polymer layers form either a cube-shaped structure or a cylinder-shaped structure.
    Type: Grant
    Filed: August 31, 2004
    Date of Patent: January 30, 2007
    Assignee: International Business Machines Corporation
    Inventors: William E. Bernier, Marie S. Cole, Mukta G. Farooq, John U. Knickerbocker, Tasha E. Lopez, Roger A. Quon, David J. Welsh
  • Patent number: 7170151
    Abstract: An LED assembly includes a heat sink and a submount. The heat sink has a top mating surface that is solder wettable, and the submount has a bottom mating surface that is solder wettable. The top and the bottom mating surfaces have substantially the same shape and area. The submount is soldered atop the heat sink. During solder reflow, the molten solder causes the submount to align with the top mating surface of the heat sink. The LED assembly may further include a substrate having a top mating surface, and the heat sink may further include a bottom mating surface. The top and bottom mating surfaces have substantially the same shape and area. The heat sink is soldered atop the substrate. During solder reflow, the molten solder causes the heat sink to align with the top mating surface of the substrate.
    Type: Grant
    Filed: January 16, 2003
    Date of Patent: January 30, 2007
    Assignee: Philips Lumileds Lighting Company, LLC
    Inventors: Cresente S. Elpedes, Zainul Fiteri bin Aziz, Paul S. Martin
  • Patent number: 7154188
    Abstract: A semiconductor chip includes a semiconductor substrate including first and second surfaces and a plurality of side surfaces, the first and second surfaces being parallel to each other and facing in opposite directions, the side surfaces connecting peripheries of the first and second surfaces. At least one of the side surfaces is an inclined surface with respect to the first and second surfaces, and a groove is formed in the inclined surface. The groove extends in a direction which intersects a plane parallel to the first and second surfaces and extends in a direction which intersects a plane which intersects the first and second surfaces at right angles.
    Type: Grant
    Filed: October 22, 2004
    Date of Patent: December 26, 2006
    Assignee: Seiko Epson Corporation
    Inventor: Yoshiharu Ogata
  • Patent number: 7138706
    Abstract: A semiconductor device with excellent heat dissipation characteristics that can achieve a high reliability when mounted in electronic equipment such as a cellular phone or the like and a method for manufacturing the same are provided. The semiconductor device includes a substrate, a plurality of semiconductor chips mounted on the substrate by stacking one on top of another, and an encapsulation resin layer made of encapsulation resin. Among the plurality of semiconductor chips, a first semiconductor chip as an uppermost semiconductor chip is mounted with a surface thereof on which a circuit is formed facing toward the substrate, and the encapsulation resin layer is formed so that at least a surface of the first semiconductor chip opposite to the surface on which the circuit is formed and a part of side surfaces of the first semiconductor chip are exposed to the outside of the encapsulation resin layer.
    Type: Grant
    Filed: June 24, 2003
    Date of Patent: November 21, 2006
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Yoshiyuki Arai, Takashi Yui, Yoshiaki Takeoka, Fumito Itou, Kouichi Yamauchi, Yasutake Yaguchi
  • Patent number: 7132743
    Abstract: This invention relates to the manufacture of a substrate, such as a package substrate or an interposer substrate, of an integrated circuit package. A base structure is formed from a green material having a plurality of via openings therein. The green material is then sintered so that the green material becomes a sintered ceramic material and the base structure becomes a sintered ceramic base structure having the via openings. A conductive via is formed in each via opening of the sintered ceramic base structure. A capacitor structure is formed on the sintered ceramic base structure. The power and ground planes of the capacitor structure are connected to the vias. As such, a capacitor structure can be formed and connected to the vias without the need to drill vias openings in brittle substrates such as silicon substrates.
    Type: Grant
    Filed: December 23, 2003
    Date of Patent: November 7, 2006
    Assignee: Intel Corporation
    Inventor: Cengiz A. Palanduz
  • Patent number: 7132755
    Abstract: An adhesive film for manufacturing a semiconductor device comprising a thermosetting adhesive layer and a heat-resistant backing layer, wherein the adhesive film is applied to a method for manufacturing a semiconductor device, comprising the steps of (a) embedding at least a part of a conductor in the adhesive film to form a conductor adhered thereto; (b) mounting a semiconductor chip on the conductor; (c) connecting the semiconductor chip to the conductor; (d) encapsulating the semiconductor chip with an encapsulation resin; and (e) removing the adhesive film therefrom. The adhesive film can be suitably used for manufacturing a semiconductor device having a so-called standoff wherein a part of a conductor is projecting from an encapsulation resin.
    Type: Grant
    Filed: December 16, 2004
    Date of Patent: November 7, 2006
    Assignee: Nitto Denko Corporation
    Inventors: Kazuhito Hosokawa, Takuji Okeyui, Kazuhiro Ikemura, Keisuke Yoshikawa
  • Patent number: 7125744
    Abstract: In the high-frequency module of the present invention, an insulating resin is formed so as to seal a high-frequency semiconductor element mounted on a surface of a substrate and further to seal electronic components. Furthermore, a metal thin film is formed on the surface of the insulating resin. This metal thin film provides an electromagnetic wave shielding effect.
    Type: Grant
    Filed: October 6, 2004
    Date of Patent: October 24, 2006
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Hideki Takehara, Noriyuki Yoshikawa, Kunihiko Kanazawa
  • Patent number: 7119372
    Abstract: A flip chip light emitting diode die (10, 10?, 10?) includes a light-transmissive substrate (12, 12?, 12?) and semiconductor layers (14, 14?, 14?) that are selectively patterned to define a device mesa (30, 30?, 30?). A reflective electrode (34, 34?, 34?) is disposed on the device mesa (30, 30?, 30?). The reflective electrode (34, 34?, 34?) includes a light-transmissive insulating grid (42, 42?, 60, 80) disposed over the device mesa (30, 30?, 30?), an ohmic material (44, 44?, 44?, 62) disposed at openings of the insulating grid (42, 42?, 60, 80) and making ohmic contact with the device mesa (30, 30?, 30?), and an electrically conductive reflective film (46, 46?, 46?) disposed over the insulating grid (42, 42?, 60, 80) and the ohmic material (44, 44?, 44?, 62). The electrically conductive reflective film (46, 46?, 46?) electrically communicates with the ohmic material (44, 44?, 44?, 62).
    Type: Grant
    Filed: October 24, 2003
    Date of Patent: October 10, 2006
    Assignee: GELcore, LLC
    Inventors: Edward B. Stokes, Mark P. D'Evelyn, Stanton E. Weaver, Peter M. Sandvik, Abasifreke U. Ebong, Xian-an Cao, Steven F. LeBoeuf, Nikhil R. Taskar
  • Patent number: 7115997
    Abstract: An integrated circuit (IC) chip, semiconductor wafer with IC chips in a number of die locations and a method of making the IC chips on the wafer. The IC chips have plated chip interconnect pads. Each plated pad includes a noble metal plated layer electroplated to a platable metal layer. The platable metal layer may be copper and the noble metal plated layer may be of gold, platinum, palladium, rhodium, ruthenium, osmium, iridium or indium.
    Type: Grant
    Filed: November 19, 2003
    Date of Patent: October 3, 2006
    Assignee: International Business Machines Corporation
    Inventors: Chandrasekhar Narayan, Kevin Shawn Petrarca
  • Patent number: 7109531
    Abstract: A high frequency switch, has a transmitting terminal, a receiving terminal, an antenna terminal, a first diode having an anode electrically connected to the transmitting terminal and a cathode electrically connected to the antenna terminal, a second diode having an anode connected through a transmission line of ΒΌ wavelength to the antenna terminal which is electrically connected to the receiving terminal, and having the side of a cathode grounded, and a control terminal provided to a node between the transmitting terminal and the first anode. The first and second diodes have a tradeoff relationship between ON resistance thereof and capacitance between the anode and the cathode, and the ON resistance of the first diode is lower than the ON resistance of the second diode, and the capacitance of the second diode in the OFF state is smaller than the capacitance of the first diode in the OFF state.
    Type: Grant
    Filed: October 28, 2004
    Date of Patent: September 19, 2006
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Shoichi Kitazawa, Masaharu Tanaka, Toshio Ishizaki, Toru Yamada
  • Patent number: 7105917
    Abstract: A semiconductor device and a fabrication method thereof are provided. The semiconductor device has a probing pad formed on a chip. The probing pad is connected to an output pad and an internal circuit though a fuse. After an electrical testing of the chip by the probing pad, the fuse is cut by a laser beam. Therefore, the probing pad is disconnected from the output pad and the internal circuit. The output pad is connected to an output lead of a package, which is encapsulating the chip. According to the device and the fabrication methods thereof, performance of the device can be enhanced by a low parasitic capacitance and a low parasitic resistance.
    Type: Grant
    Filed: September 13, 2001
    Date of Patent: September 12, 2006
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Kang-Sik Cho, Chul-Sung Park, Gyu-Chul Kim
  • Patent number: 7102209
    Abstract: A lead-frame based substrate panel for use in semiconductor packaging is described. The substrate panel includes a lead-frame panel having at least one array of device areas. Each device area has a plurality of contacts. The lead-frame panel is filled with a dielectric material to form a relatively rigid substrate panel that can be used for packaging integrated circuits. The top surface of the dielectric material is typically substantially coplanar with the top surface of the lead-frame panel, and the bottom surface of the dielectric material is typically substantially coplanar with the bottom surface of the lead-frame panel.
    Type: Grant
    Filed: August 27, 2003
    Date of Patent: September 5, 2006
    Assignee: National Semiconductor Corporation
    Inventors: Jaime Bayan, Ashok S. Prabhu, Fred Drummond
  • Patent number: 7102230
    Abstract: A circuit carrier adapted for a pin grid array (PGA) package is disclosed. The circuit carrier comprises a substrate, at least one pin pad, at least one solder mask layer, at least one solder layer, at least one pin and a fixing layer. The pin pad is disposed over the surface of the substrate. The solder mask layer is disposed over the surface of the substrate, and exposing at least a portion of the pin pad. The solder layer is disposed over the pin pad. One end of the pin connects to the pin pad through the solder layer. The fixing layer is disposed over the solder mask layer, and covering the solder layer and a portion of a side surface of the pin. When the solder layer melts due to a high process temperature, the fixing layer helps to fix the pin to the pin pad.
    Type: Grant
    Filed: November 18, 2004
    Date of Patent: September 5, 2006
    Assignee: VIA Technologies, Inc.
    Inventor: Chih-An Yang
  • Patent number: 7091582
    Abstract: A semiconductor device package comprises a perimeter wall snap fitted to a base having a semiconductor die mounted on the base. A lead is mounted on the opposite side of the die, and the die and a portion of the lead are protected by an encapsulant disposed within the perimeter wall.
    Type: Grant
    Filed: November 17, 2003
    Date of Patent: August 15, 2006
    Inventors: Mario Merlin, Sebastiano Ferrero
  • Patent number: 7053495
    Abstract: A semiconductor integrated circuit device includes: Si substrate; multilevel interconnect layer formed on the Si substrate; and dielectric layer formed on the multilevel interconnect layer. External-component-connecting wire, ordinary wire, fuse wire, stepper alignment mark, and target mark are formed out of an identical copper film in the uppermost metal layer. External-component-connecting pad electrode, testing-processing alignment mark, and stepper alignment mark are formed out of an identical aluminum alloy film on the dielectric film. In laser-machining the fuse wire, alignment using the target mark formed in the metal layer including the fuse wire reduces alignment errors caused from the machining.
    Type: Grant
    Filed: September 16, 2002
    Date of Patent: May 30, 2006
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventor: Katsuhiko Tsuura
  • Patent number: 7042103
    Abstract: A semiconductor device (121) is provided which comprises a substrate and a die (123) having a first surface which is attached to the substrate by way of a die attach material. At least a portion (127) of the perimeter of the die is resistant to wetting by the die attach material, either through treatment with a dewetting agent or by selective removal of the backside metallization. It is found that this construction allows the surface area of the die to be increased without increasing the incidence of cracking and chipping along the sawn edges of the die.
    Type: Grant
    Filed: December 30, 2002
    Date of Patent: May 9, 2006
    Assignee: Motorola, Inc.
    Inventors: Brian W. Condie, David J. Dougherty
  • Patent number: 7038291
    Abstract: Provided is a semiconductor device and a method of fabricating the semiconductor device, in which electric characteristics of a gate insulating film thereof in the vicinity of an element isolation region are equal to electric characteristics of the gate insulating film at portions other than the vicinity of the element isolation region. A semiconductor device of the present invention includes a semiconductor substrate, shallow trench isolation regions formed in the semiconductor substrate, source and drain regions formed in the semiconductor substrate, the source and drain regions sandwiching a surface of the semiconductor substrate to define a channel, gate insulating films having equal thicknesses in a central portion of the channel and in portions contacting with on the shallow trench isolation regions, and gate electrodes formed on the gate insulating films.
    Type: Grant
    Filed: January 30, 2002
    Date of Patent: May 2, 2006
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Akira Goda, Mitsuhiro Noguchi, Hiroaki Hazama
  • Patent number: 6825520
    Abstract: A process for creating a storage node electrode, for a DRAM cell, exhibiting increased surface area resulting from the formation of an agglomerated metal silicide layer, on the top surface of the storage node electrode, has been developed. The process features creating a polysilicon, storage node electrode shape, followed by the formation of an overlying, agglomerated titanium disilicide layer. The agglomerated titanium disilicide layer is formed from a RTA procedure, applied to a smooth titanium disilicide layer, located on the polysilicon, storage node electrode.
    Type: Grant
    Filed: March 27, 2000
    Date of Patent: November 30, 2004
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: Shau-Lin Shue, Cheng-Yeh Shih
  • Patent number: 6812515
    Abstract: A non-volatile memory cell includes a first insulating layer over a substrate region, and a floating gate. The floating gate includes a first polysilicon layer over the first insulating layer and a second polysilicon layer over and in contact with the first polysilicon layer. The first polysilicon layer has a predetermined doping concentration and the second polysilicon layer has a doping concentration which decreases in a direction away from an interface between the first and second polysilicon layers. A second insulating layer overlies and is in contact with the second polysilicon layer. A control gate includes a third polysilicon layer over and in contact with the second insulating layer, and a fourth polysilicon layer over and in contact with the third polysilicon layer. The fourth polysilicon layer has a predetermined doping concentration, and the third polysilicon layer has a doping concentration which decreases in a direction away from an interface between the third and fourth polysilicon layers.
    Type: Grant
    Filed: November 26, 2001
    Date of Patent: November 2, 2004
    Assignee: Hynix Semiconductor, Inc.
    Inventors: Peter Rabkin, Hsingya Arthur Wang, Kai-Cheng Chou