Abstract: A power DMOS transistor having an improved current driving capability and improved reliability is provided. A fabrication method thereof is also provided. The DMOS transistor includes a semiconductor substrate having a first conductivity type and a semiconductor region having a second conductivity type formed on the semiconductor substrate. A drain having a second conductivity type is formed on the semiconductor region. A high-concentration buried impurity layer having a second conductivity type is formed on the semiconductor region under the drain. A body region having a first conductivity type is formed in the semiconductor substrate spaced a predetermined distance from the semiconductor region. A source having a second conductivity type is formed on the body region. A gate electrode is formed on the semiconductor substrate having a gate insulative film formed thereon. A source electrode and a drain electrode coupled respectively to the source and the drain are formed on the resultant structure.

Abstract: An improved fin device used as the body of a field effect transistor (“FET”) and an improved process of making the fin device. The fin device allows for the fabrication of very small dimensioned metal-oxide semiconductor (“MOS”) FETs in the size range of micrometers to nanometers, while avoiding the typical short channel effects often associated with MOSFETs of these dimensions. Accordingly, higher density MOSFETs may be fabricated such that more devices may be placed on a single semiconductor wafer. The process of making the fin device results in an improved fully planarized device.

Abstract: An apparatus and a method for providing a heat sink on an upper surface of a semiconductor chip by placing a heat-dissipating material thereon which forms a portion of a glob top. The apparatus comprises a semiconductor chip attached to and in electrical communication with a substrate. A barrier glob top material is applied to the edges of the semiconductor chip on the surface (“opposing surface”) opposite the surface attached to the substrate to form a wall around a periphery of an opposing surface of the semiconductor chip wherein the barrier glob top material also extends to contact and adhere to the substrate. The wall around the periphery of the opposing surface of the semiconductor chip forms a recess. A heat-dissipating glob top material is disposed within the recess to contact the opposing surface for the semiconductor chip.

Abstract: A method of manufacturing semiconductor components includes etching two trenches (105, 106, 805, 806, 1205, 1206) into a surface of a substrate (101, 801, 1201), lining the two trenches (105, 106, 805, 806, 1205, 1206) with an electrically insulative layer (107, 807, 1207) that is never completely removed from a first one of the two trenches (105, 106, 805, 806, 1205, 1206), and simultaneously filling the two trenches (105, 106, 805, 806, 1205, 1206) with a material wherein the material is never completely removed from the first one of the two trenches (105, 106, 805, 806, 1205, 1206) and wherein the second one of the two trenches (105, 106, 805, 806, 1205, 1206) becomes electrically coupled to the substrate (101, 801, 1201).

Abstract: A mold 25 for molding semiconductor chips 23 and 24 serving as a light emitting element and a light receiving element, respectively, is made of a material capable of transmitting light. A groove 27 is formed on the region where light is emitted from and incident on the semiconductor chips so that it constitutes a reflecting face. Thus, the light is emitted and incident through the side E of the mold. In this configuration, the outer size of the light receiving element or light emitting element can be minimized, and the module provided with these semiconductor chips can also be miniaturized.

Abstract: An integrated circuit capacitor includes a first dielectric layer adjacent a substrate and having a trench therein, and a metal plug comprising an upper portion extending upwardly into the trench, and a lower portion disposed in the first dielectric layer. The lower portion has a tapered width which increases in a direction toward the substrate to thereby secure the metal plug in the dielectric layer. Preferably, the upper portion is also tapered. Furthermore, a second dielectric layer is adjacent the metal plug with an upper electrode thereon.

Abstract: A method and lateral bipolar transistor structure are achieved, with high current gain, compatible with CMOS processing to form BiCMOS circuits. Making a lateral PNP bipolar involves forming an N− well in a P− doped silicon substrate. A patterned Si3N4 layer is used as an oxidation barrier mask to form field oxide isolation around device areas by the LOCOS method. A polysilicon layer over device areas is patterned to leave portions over the intrinsic base areas of the L-PNP bipolar an implant block-out mask. A buried N− base region is implanted in the substrate under the emitter region. A photoresist mask and the patterned polysilicon layer are used to implant the P++ doped emitter and collector for the L-PNP. The emitter junction depth xj intersects the highly doped N+ buried base region. This N+ doped base under the emitter reduces the current gain of the unwanted (parasitic) vertical PNP portion of the L-PNP bipolar to reduce the current gain of the V-PNP.

Abstract: In a chip package, when a Ni/Au layer is formed by electroless plating, there is no problem with density increasing of interconnections and the like, since leads for plating and tie bars are not formed. However, the adhesive strength of solder balls to ball pads is low, so that the adhesion tends to be unstable. In the present invention, no leads for plating are formed, while the adhesive strength of solder balls to ball pads is improved by electroplating the ball pads with a Ni/Au layer. In addition, an increase in the density of interconnections and an improvement of the electrical properties is also obtained. The Ni/Au layer is formed by electroplating on the base metal layer surface which is not covered with a DFR (Dry Film Resist) by applying an electric current to the base metal layer.

Abstract: An apparatus for detecting energy and point of incidence of an ionizing event comprising a semiconductor layer with a first type of conductivity, in which at least one first doped region with the first type of conductivity and a corresponding plurality of second doped regions with a second type of conductivity associated to said at least one first doped region are formed on a first surface of said layer, said at least first doped region and said corresponding plurality of second doped regions defining a respective drift path for charge carriers with the first type of conductivity, and at least one third doped region with the second type of conductivity is formed on a second surface of said layer, and means for biasing said second doped regions and said third doped region which is capable of reversely biasing the junctions between the second doped regions and the semiconductor layer and between the third doped region and the semiconductor layer so as to deplete the semiconductor layer.

Abstract: A hydrogen barrier encapsulation technique for the control of hydrogen induced degradation of ferroelectric capacitors in non-volatile integrated circuit memory devices. The resultant device structure ameliorates the hydrogen induced degradation of ferroelectric capacitors by completely encapsulating the capacitor within a suitable hydrogen barrier material, such as chemical vapor deposition (“CVD”) or sputtered silicon nitride, thus ensuring process compatibility with industry standard process steps. Although the deposition process for CVD Si3N4 itself contains hydrogen, the deposition time may be kept relatively short thereby allowing the TiN local interconnect layer to act as a “short term” hydrogen barrier.

Abstract: A semiconductor device and fabrication process are provided in which a patterned metal layer is formed over a polysilicon line. The polysilicon line is disposed on a substrate and may, for example, be a gate electrode. A dielectric layer is disposed adjacent the polysilicon line and the patterned metal layer is formed over the polysilicon line. The device may further include a second polysilicon line, such as a gate electrode, and the patterned metal layer may extend over the top of the second polysilicon line and interconnect the two polysilicon lines. A contact for the polysilicon line is coupled to the patterned metal layer. The use of a patterned metal line may provide a larger footprint for the contact then the underlying polysilicon line(s) and may decrease the sheet resistance to the polysilicon line(s).

Abstract: A semiconductor device includes a lead frame, a dielectric tape layer, a plurality of conductive contacts and a semiconductor die. The lead frame is provided with a plurality of leads. The dielectric tape layer has a first adhesive surface adhered onto the leads, and a second adhesive surface opposite to the first adhesive surface. The dielectric tape layer is formed with a plurality of holes at positions registered with the leads for access thereto. Each of the holes is confined by a wall that cooperates with a registered one of the leads to form a contact receiving space. The conductive contacts are placed in the contact receiving spaces, respectively. The die has a die mounting surface adhered onto the second adhesive surface of the dielectric tape layer. The die mounting surface is provided with a plurality of contact pads that are bonded to the conductive contacts to establish electrical connection with the leads of the lead frame. A method for fabricating the semiconductor device is also disclosed.

Abstract: A method of producing a semiconductor device having a heat dissipating metal layer wherein the number of patterning steps is reduced, laser dicing produces a better profile, and first and second metal layers are prevented from separating from each other, and a semiconductor device produced by the method. The number of patterning steps is reduced by employing a flat exposure step for photoresist with mask alignment. A better appearance is obtained by forming the metal layers which connect the semiconductor devices with each other from a first metal layer having a lower melting point and a second metal layer having a higher melting point and severing the first metal layer and the second metal layer successively, from the first metal layer side. A second metal layer is prevented from peeling by preventing oxidation of the plated feeder layer through plating of the second metal layer.

Abstract: A solid-state imaging sensor, a method for manufacturing the solid-state imaging sensor and an imaging device of which said solid state image sensor is designed to reduce unwanted light reflections, improve light focusing of light reflections from the substrate and oblique light constituents onto the sensor in order to allow further reduction in pixel size. Transfer electrodes in a line shape are arrayed at spaced intervals on a substrate, discrete sensors for photo-electric conversion are formed between the transfer electrode lines, a light-impervious film consisting of a first and second light-impervious films with an aperture positioned directly above a sensor is formed on the substrate and covers the transfer electrode to block any incident light other than the beam of light R from entering the sensor, and an on-chip lens for focusing the light R onto a sensor is formed above the light-impervious film.

Abstract: A power trench MOS-gated transistor is constructed with a buried gate to source dielectric inside a gate trench region. In the innovative device, a thick oxide (grown or deposited) is used to define the height of the trench walls. A body region is initially formed by selective epitaxial growth and etch back. Source regions are formed also by selective epitaxial growth. The body is finally formed by selective epitaxial growth and etch back. The oxide is removed from the trench, the trench walls are oxidized to form a gate oxide, and doped polysilicon fills the trench to form a gate. By the formation of the source region using the spacer etch, this process simplifies the fabrication of power trench gated devices, and provides for increased contact surface area without increasing device size.

Abstract: A lower electrode of a capacitor is formed by a cylindrical conductive film and a pillar shaped conductive film disposed coaxially within the cylindrical conductive film. Consequently, in this capacitor, even if a plane area of the lower electrode is so small that double cylinder type cannot be realized, opposing area of the lower electrode and upper electrode is larger as compared to a structure in which the lower electrode is of single cylinder type. This invention proposes such a capacitor and a method of manufacturing thereof. As a result, it is possible to increase electric storage capacity if the plane area of the capacitor is the same and further miniaturize the capacitor if the electric storage capacity is the same.

Abstract: A pair of substrates forming the active matrix liquid crystal display are fabricated from resinous substrates having transparency and flexibility. A thin-film transistor has a semiconductor film formed on a resinous layer formed on one resinous substrate. The resinous layer is formed to prevent generation of oligomers on the surface of the resinous substrate during formation of the film and to planarize the surface of the resinous substrate.

Abstract: The present invention relates to a capacitor and a method of fabricating the same including a semiconductor substrate, an impurity region in the semiconductor substrate, a first insulating layer on the semiconductor substrate, the first insulating layer having a first contact hole to expose the impurity region, a first conductive layer in the contact hole, a second conductive layer on the first insulating layer, a second insulating layer on the first insulating layer including the second conductive layer, the second insulating layer contacting the first portion of the second conductive layer, a lower electrode on the second insulating layer, the lower electrode being not directly contacting the first conductive layer, a dielectric layer on the lower electrode including the second insulating layer, and an upper electrode on the dielectric layer.

Abstract: The projection optical system of a projection aligner has a lens barrel, a plurality of lenses arranged in the lens barrel, and pressure adjusting apparatuses coupled to the inner spaces of lens barrel separated by the lenses. The pressure adjusting apparatuses adjust the pressures in the inner spaces to cancel the weight of the lenses themselves. Thus, the projection aligner capable of forming a highly-accurate and fine pattern by suppressing occurrence of aberration due to the weight of the optical member and the exposure method using the same are obtained.

Abstract: Disclosed is a GaN-based compound semiconductor light-emitting element, comprising an AlN buffer layer, a GaN lattice strain moderating layer, and an n-type AlGaN contact layer formed on the layer. The GaN lattice strain moderating layer has a lattice constant larger than that of the AlN buffer layer. On the other hand, the contact layer has a lattice constant smaller than that of the AlN buffer layer. Further, the GaN lattice strain moderating layer has a thickness falling within a range of between 0.01 &mgr;m to 0.5 &mgr;m.