Patents Examined by Eddie P. Chan
  • Patent number: 9207958
    Abstract: In one general aspect, a system includes an abstract machine instruction stream, a virtual machine coprocessor configured to receive an instruction from the abstract machine instruction stream and to generate one or more native machine instructions in response to the received instruction, and a processor coupled to the virtual machine coprocessor and operable to execute the native machine instructions generated by the virtual machine coprocessor. The virtual machine coprocessor is operable to generate one or more native machine instructions to explicitly control the virtual machine coprocessor.
    Type: Grant
    Filed: August 8, 2003
    Date of Patent: December 8, 2015
    Assignee: ARM FINANCE OVERSEAS LIMITED
    Inventor: Kevin D. Kissell
  • Patent number: 8627313
    Abstract: A data center can share processing resources using virtual networks. A hosting program 9,10 hosts one or more virtual machines 11, 12. The program has a virtual interface VIF 1 14, to the virtual machines, a network interface 19 to enable communication between the virtual machines and other nodes of a network, and an infrastructure management interface 8, invisible to the virtual machines. The program has an intercept function 7 implemented as a comparator, switch or router, arranged to intercept a status message from one of the virtual machines, or applications run by that virtual machine. The status indication is sent to a status buffer 5 and is made available to the infrastructure management interface without providing a network path between the management interface and the virtual machine. This can discriminate between VM failure and communication failure, and the invisibility maintains isolation and helps avoid vulnerability to denial of service attack.
    Type: Grant
    Filed: March 9, 2009
    Date of Patent: January 7, 2014
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Aled Edwards, Anna Fischer, Patrick Goldsack
  • Patent number: 8555290
    Abstract: A task count controller, a task count control method, and a computer program capable of dynamically controlling the number of tasks that can be processed in parallel simultaneously without increasing computational load are provided. When a plurality of tasks are to be executed simultaneously in parallel processing, the number of tasks that can be executed simultaneously is controlled. The tasks to be executed simultaneously are added in units of a predetermined number of tasks and the throughput in one unit of work is measured for each task every time the tasks are added. The total sum of the measured throughputs is calculated, and it is determined whether the calculated total sum of throughputs is more than the total sum of throughputs immediately before the predetermined number of tasks are added.
    Type: Grant
    Filed: March 16, 2009
    Date of Patent: October 8, 2013
    Assignee: International Business Machines Corporation
    Inventors: Fumitaka Uruma, Yoshiko Yaegashi
  • Patent number: 8438566
    Abstract: Automated management of partition service assignment to a virtual input/output (VIO) adapter is provided. Responsive to creation of a new partition service in a data processing system, a partition priority number is determined for the new partition service, and, for each VIO adapter, the partition priority numbers of the partition services currently assigned to that VIO adapter are summed. For a VIO adapter with a lowest sum of partition priority numbers, logic determines whether assigning the new partition service to that VIO adapter results in its summed partition priority number being above a predefined threshold, and the new partition service is assigned to a VIO adapter based, at least in part, on whether assigning the new partition service to the VIO adapter with the lowest sum of partition priority numbers results in that VIO adapter's summed partition priority number exceeding the predefined threshold.
    Type: Grant
    Filed: April 16, 2012
    Date of Patent: May 7, 2013
    Assignee: International Business Machines Corporation
    Inventors: Bryan M. Logan, Kyle A. Lucke, Amartey S. Pearson, Steven E. Royer
  • Patent number: 8429382
    Abstract: A symmetric multi-processing (SMP) processor includes a primary interconnect trunk for communication of information between multiple compute elements situated along the primary interconnect trunk. The processor also includes a secondary interconnected trunk that may be oriented perpendicular with respect to the primary interconnect trunk. The processor distributes data on-ramps and data off-ramps across the data lanes of a data trunk of the primary interconnect trunk to enable communication with compute elements and other structures both on-chip and off-chip.
    Type: Grant
    Filed: April 30, 2008
    Date of Patent: April 23, 2013
    Assignee: International Business Machines Corporation
    Inventors: Robert Alan Cargnoni, Gary Alan Gorman, Charles Francis Marino, Julie Ann Rosser
  • Patent number: 8429386
    Abstract: Various techniques for dynamically allocating instruction tags and using those tags are disclosed. These techniques may apply to processors supporting out-of-order execution and to architectures that supports multiple threads. A group of instructions may be assigned a tag value from a pool of available tag values. A tag value may be usable to determine the program order of a group of instructions relative to other instructions in a thread. After the group of instructions has been (or is about to be) committed, the tag value may be freed so that it can be re-used on a second group of instructions. Tag values are dynamically allocated between threads; accordingly, a particular tag value or range of tag values is not dedicated to a particular thread.
    Type: Grant
    Filed: June 30, 2009
    Date of Patent: April 23, 2013
    Assignee: Oracle America, Inc.
    Inventors: Paul J. Jordan, Robert T. Golla, Jama I. Barreh
  • Patent number: 8429662
    Abstract: A computer program product for passing initiative in a multitasking multiprocessor environment includes a tangible storage medium readable by a processing circuit and storing instructions for execution by the processing circuit for performing a method. The method includes writing a request to process a resource of the environment to an associated resource control block, setting a resource flag in a central bit vector, the resource flag indicating that a request for processing has been received for the resource, and setting a target processor initiative flag in the environment, the target processor initiative flag indicating a pass of initiative to a target processor responsible for the resource.
    Type: Grant
    Filed: March 28, 2008
    Date of Patent: April 23, 2013
    Assignee: International Business Machines Corporation
    Inventors: Leonard W. Helmer, Jr., John S. Houston, Ambrose A. Verdibello, Jr.
  • Patent number: 8424007
    Abstract: A computer-implemented method for prioritizing virtual machine tasks may include receiving a request to perform a first task from a virtual machine. The request may include information relevant to determining a priority of the task. The method may include determining the priority of the task based on the information. The method may further include scheduling the first task based on the priority of the task. The method may include selecting the first task for execution based on the scheduling. The method may include notifying the virtual machine that the first task has been selected for execution. Various related methods, computer-readable media, and systems are also disclosed.
    Type: Grant
    Filed: September 30, 2008
    Date of Patent: April 16, 2013
    Assignee: Symantec Corporation
    Inventors: Brian Hernacki, Sourabh Satish, William E. Sobel
  • Patent number: 8417917
    Abstract: A mechanism is provided for improving the performance and efficiency of multi-core processors. A system controller in a data processing system determines an operational function for each primary processor core in a set of primary processor cores in a primary processor core logic layer and for each secondary processor core in a set of secondary processor cores in a secondary processor core logic layer, thereby forming a set of determined operational functions. The system controller then generates an initial configuration, based on the set of determined operational functions, for initializing the set of primary processor cores and the set of secondary processor cores in the three-dimensional processor core architecture. The initial configuration indicates how at least one primary processor core of the set of primary processor cores collaborate with at least one secondary processor core of the set of secondary processor cores.
    Type: Grant
    Filed: September 30, 2009
    Date of Patent: April 9, 2013
  • Patent number: 8417923
    Abstract: A data processing apparatus is disclosed including trace logic for monitoring behavior of a portion of said data processing apparatus and prediction logic for providing at least one prediction as to at least one step of the behavior of the portion of the data processing apparatus. The trace logic monitors behavior of the portion of the data processing apparatus, determines from the monitored behavior whether the at least one prediction is correct, and outputs a prediction indicator indicating whether the at least one prediction is correct.
    Type: Grant
    Filed: June 1, 2010
    Date of Patent: April 9, 2013
    Assignee: ARM Limited
    Inventors: Michael John Williams, John Michael Horley, Edmond John Simon Ashfield
  • Patent number: 8407454
    Abstract: There is provided a method and processor for processing a thread. The thread comprises a plurality of sequential instructions, the plurality of sequential instructions comprising some short-latency instructions and some long-latency instructions and at least one hazard instruction, the hazard instruction requiring one or more preceding instructions to be processed before the hazard instruction is processed. The method comprises the steps of: a) before processing each long-latency instruction, incrementing by one, a counter associated with the thread; b) after each long-latency instruction has been processed, decrementing by one, the counter associated with the thread; c) before processing each hazard instruction, checking the value of the counter associated with the thread, and i) if the counter value is zero, processing the hazard instruction, or ii) if the counter value is non-zero, pausing processing of the hazard instruction until a later time.
    Type: Grant
    Filed: June 3, 2012
    Date of Patent: March 26, 2013
    Assignee: Imagination Technologies, Ltd.
    Inventors: Morrie Berglas, Yoong Chert Foo
  • Patent number: 8407455
    Abstract: A computer-implemented method and article of manufacture is disclosed for enabling computer programs utilizing hardware transactional memory to safely interact with code utilizing traditional locks. A thread executing on a processor of a plurality of processors in a shared-memory system may initiate transactional execution of a section of code, which includes a plurality of access operations to the shared-memory, including one or more to locations protected by a lock. Before executing any operations accessing the location associated with the lock, the thread reads the value of the lock as part of the transaction, and only proceeds if the lock is not held. If the lock is acquired by another thread during transactional execution, the processor detects this acquisition, aborts the transaction, and attempts to re-execute it.
    Type: Grant
    Filed: July 28, 2009
    Date of Patent: March 26, 2013
    Assignee: Advanced Micro Devices, Inc.
    Inventors: David S. Christie, Michael P. Hohmuth, Stephan Diestelhorst
  • Patent number: 8407700
    Abstract: A computer-implemented method may include identifying first and second sublayers of a virtualized application. The first and/or second virtualization sublayers may include a read-write sublayer, a read-only sublayer, a virtual-reset-point sublayer, and/or a patch sublayer. The computer-implemented method may also include merging an instance of the first virtualization sublayer with an instance of the second virtualization sublayer. Various other methods, systems, and computer-readable media are also disclosed.
    Type: Grant
    Filed: March 3, 2009
    Date of Patent: March 26, 2013
    Assignee: Symantec Corporation
    Inventors: Karl Bunnell, Paul Mackay, Jared Payne
  • Patent number: 8407451
    Abstract: An information handling system includes a processor with multiple hardware units that generate program application load, store, and I/O interface requests to system busses within the information handling system. The processor includes a resource allocation identifier (RAID) that links the processor hardware unit initiating a system bus request with a specific resource allocation group. The resource allocation group assigns a specific bandwidth allocation rate to the initiating processor. When a load, store, or I/O interface bus request reaches the I/O bus for execution, the resource allocation manager restricts the amount of bandwidth associated with each I/O request by assigning discrete amounts of bandwidth to each successive I/O requester. Successive stages of the instruction pipeline in the hardware unit contain the resource allocation identifiers (RAID) linked to the specific load, store, or I/O instruction.
    Type: Grant
    Filed: February 6, 2007
    Date of Patent: March 26, 2013
    Assignee: International Business Machines Corporation
    Inventors: Gavin Balfour Meil, Steven Leonard Roberts, Christopher John Spandikow
  • Patent number: 8407457
    Abstract: A system has a pipelined processor for executing a plurality of instructions by sequentially fetching, decoding, executing and writing results associated with execution of each instruction. Debug circuitry is coupled to the pipelined processor for monitoring execution of the instructions to determine when a debug event occurs. The debug circuitry generates a debug exception to interrupt instruction processing flow. The debug circuitry has control circuitry for indicating a number of instructions, if any, that complete instruction execution between an instruction that caused the debug event and a point in instruction execution when the exception is taken.
    Type: Grant
    Filed: September 28, 2007
    Date of Patent: March 26, 2013
    Assignee: Freescale Semiconductor, Inc.
    Inventor: William C. Moyer
  • Patent number: 8381221
    Abstract: Method, computer program products and systems for conserving energy in data processing center, wherein a plurality of services are offered to a plurality of subscribed service consumers in a dynamic fashion, allowing a created service instance to be re-assigned from one to another server of the resources. Control parameters comprising power consumption and temperature of a group of resources are monitored. A workload may be assigned properties such as “hot” and “cold.” which are then assessed. A hot workload may be relocated to a cold spot, and if necessary, a cold workload may be relocated to a location which was de-loaded from a workload, that is, a hot spot, which is then considered to cool down due to addition of less workload in form of the cold workload. Thus, the energy required to cool the data center may be minimized.
    Type: Grant
    Filed: March 3, 2009
    Date of Patent: February 19, 2013
    Assignee: International Business Machines Corporation
    Inventors: Michael Behrendt, Andreas Bieswanger, Gerd Breiter, Hans-Deiter Wehle
  • Patent number: 8380964
    Abstract: An information handling system includes a processor with an instruction issue queue (IQ) that may perform age tracking operations. The issue queue IQ maintains or stores instructions that may issue out-of-order in an internal data store IDS. The IDS organizes instructions in a queue position (QPOS) addressing arrangement. An age matrix of the IQ maintains a record of relative instruction aging for those instructions within the IDS. The age matrix updates latches or other memory cell data to reflect the changes in IDS instruction ages during a dispatch operation into the IQ. During dispatch of one or more instructions, the age matrix may update only those latches that require data change to reflect changing IDS instruction ages. The age matrix employs row and column data and clock controls to individually update those latches requiring update.
    Type: Grant
    Filed: April 3, 2009
    Date of Patent: February 19, 2013
    Assignee: International Business Machines Corporation
    Inventors: James Wilson Bishop, Mary Douglass Brown, Jeffrey Carl Brownscheidle, Robert Allen Cordes, Maureen Anne Delaney, Jafar Nahidi, Dung Quoc Nguyen, Joel Abraham Silberman
  • Patent number: 8370608
    Abstract: The described embodiments provide a processor for generating a result vector with copied or propagated values from an input vector. During operation, the processor receives at least one input vector and a control vector. Using these vectors, the processor generates the result vector, which can contain copied propagated values from the input vector(s), depending on the value of the control vector. In addition, a predicate vector can be used to control the values that are written to the result vector.
    Type: Grant
    Filed: June 30, 2009
    Date of Patent: February 5, 2013
    Assignee: Apple Inc.
    Inventors: Jeffry E. Gonion, Keith E. Diefendorff
  • Patent number: 8370834
    Abstract: A data center can share processing resources using virtual networks. A virtual machine manager (10) hosts one or more virtual machines (11, 411), the virtual machines forming part of a segmented virtual network (34). Outgoing messages from the virtual machines have an intermediate destination address of an intermediate node in a local segment of the segmented virtual network, and the virtual machine manager has a router (18) for determining a new intermediate destination address outside the local segment, for routing the given outgoing message. By having the router as part of the virtual machine manager rather than having only a switch in the virtual machine manager, the need for virtual machines for implementing gateways is avoided. This can reduce the number of “hops” for the message between virtual entities hosted, and thus improve performance. This can help a service provider to share physical processing resources of a data center between different clients having their own virtual networks.
    Type: Grant
    Filed: March 9, 2009
    Date of Patent: February 5, 2013
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Aled Edwards, Anna Fischer, Chris I Dalton, Patrick Goldsack
  • Patent number: 8365175
    Abstract: One embodiment provides a method of managing power in a datacenter having a plurality of servers. A number of policy settings are specified for the power center, including a power limit for the datacenter. The power consumption attributable to each of a plurality of applications executable as a job on one or more of the servers is determined. The power consumption attributable to each application may be further qualified according to the type of server on which the application is executed. Having determined the power consumption attributable to various applications executable as jobs, the applications may be executed on the servers as jobs such that the total power consumption attributable to the currently executed jobs remains within the selected datacenter power limit.
    Type: Grant
    Filed: March 10, 2009
    Date of Patent: January 29, 2013
    Assignee: International Business Machines Corporation
    Inventor: Srihari Venkata Angaluri