Patents Examined by Eddie P. Chan
  • Patent number: 8359457
    Abstract: The semiconductor device includes a controller and a plurality of dynamically reconfigurable circuits connected to one another in series below the controller to perform operations in the manner of a pipeline. The controller inputs data and reconfiguration information to the first one of the dynamically reconfigurable circuits. Each of the dynamically reconfigurable circuits includes a processing unit that performs a data computation, an updating unit that updates the reconfiguration information, and a repetition controlling unit that determines whether to repeat the computation and controls the data and the reconfiguration information.
    Type: Grant
    Filed: February 17, 2009
    Date of Patent: January 22, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Takashi Yoshikawa, Shigehiro Asano
  • Patent number: 8356163
    Abstract: A disclosed SIMD microprocessor includes plural processor elements each having n arithmetic circuits and n registers configured to temporarily store data pieces to be input to the arithmetic circuits, n being a natural number equal to or greater than 2, and; a control circuit configured to determine an arrangement order of the processor elements and an arrangement order of the arithmetic circuits in the processor elements and determine whether to use the n arithmetic circuits as a single arithmetic circuit or as n arithmetic circuits. Each processor element further includes n shifter pairs each including a PE shifter and a bit shifter; and n shift data selection circuits configured to select arbitrary data pieces from the data pieces in the shifter pairs, perform bit extension on the data pieces, and transfer the data pieces to the arithmetic circuits.
    Type: Grant
    Filed: June 24, 2008
    Date of Patent: January 15, 2013
    Assignee: Ricoh Company, Ltd.
    Inventor: Toshiki Yamanaka
  • Patent number: 8356164
    Abstract: The described embodiments provide a processor for generating a result vector with shifted values from an input vector. During operation, the processor receives an input vector and a control vector. Using these vectors, the processor generates the result vector, which can contain shifted values or propagated values from the input vector, depending on the value of the control vector. In addition, a predicate vector can be used to control the values that are written to the result vector.
    Type: Grant
    Filed: June 30, 2009
    Date of Patent: January 15, 2013
    Assignee: Apple Inc.
    Inventors: Jeffry E. Gonion, Keith E. Diefendorff
  • Patent number: 8356166
    Abstract: Minimizing code duplication in an unbounded transactional memory system. A computing apparatus including one or more processors in which it is possible to use a set of common mode-agnostic TM barrier sequences that runs on legacy ISA and extended ISA processors, and that employs hardware filter indicators (when available) to filter redundant applications of TM barriers, and that enables a compiled binary representation of the subject code to run correctly in any of the currently implemented set of transactional memory execution modes, including running the code outside of a transaction, and that enables the same compiled binary to continue to work with future TM implementations which may introduce as yet unknown future TM execution modes.
    Type: Grant
    Filed: June 26, 2009
    Date of Patent: January 15, 2013
    Assignee: Microsoft Corporation
    Inventors: Ali-Reza Adl-Tabatabai, Bratin Saha, Gad Sheaffer, Vadim Bassin, Robert Y. Geva, Martin Taillefer, Darek Mihocka, Burton Jordan Smith, Jan Gray
  • Patent number: 8352711
    Abstract: The coordination and execution of chores in a multiprocessing environment. The coordination of chores is accomplished utilizing a compiler generated correlation that relates blocks of code that execute chores and blocks of code in which the chore can be realized. By tracking the execution of the program and using the compiler-generated correlation, chores can be identified for the currently executing code.
    Type: Grant
    Filed: January 22, 2008
    Date of Patent: January 8, 2013
    Assignee: Microsoft Corporation
    Inventors: Eric Dean Tribble, Mark Ronald Plesko, Christopher Wellington Brumme
  • Patent number: 8335910
    Abstract: An apparatus extracts instructions from a stream of undifferentiated instruction bytes in a microprocessor having an instruction set architecture in which the instructions are variable length. Decoders generate an associated start/end mark for each instruction byte of a line from a first queue of entries each storing a line of instruction bytes. A second queue has entries each storing a line received from the first queue along with the associated start/end marks.
    Type: Grant
    Filed: October 1, 2009
    Date of Patent: December 18, 2012
    Assignee: VIA Technologies, Inc.
    Inventor: Thomas C. McDonald
  • Patent number: 8335911
    Abstract: Systems and methods for efficient dynamic utilization of shared resources in a processor. A processor comprises a front end pipeline, an execution pipeline, and a commit pipeline, wherein each pipeline comprises a shared resource with entries configured to be allocated for use in each clock cycle by each of a plurality of threads supported by the processor. To avoid starvation of any active thread, the processor further comprises circuitry configured to ensure each active thread is able to allocate at least a predetermined quota of entries of each shared resource. Each pipe stage of a total pipeline for the processor may include at least one dynamically allocated shared resource configured not to starve any active thread. Dynamic allocation of shared resources between a plurality of threads may yield higher performance over static allocation. In addition, dynamic allocation may require relatively little overhead for activation/deactivation of threads.
    Type: Grant
    Filed: September 30, 2009
    Date of Patent: December 18, 2012
    Assignee: Oracle America, Inc.
    Inventors: Robert T. Golla, Gregory F. Grohoski
  • Patent number: 8332829
    Abstract: Within a data processing system, one or more register files are assigned to respective states of a graph for each of a plurality of clock cycles. A plurality of edges are inserted to form connections between the states of the graph, with respective weights being assigned to each of the edges. A best route through the graph is then determined based, at least in part, on the weights assigned to the edges.
    Type: Grant
    Filed: August 15, 2008
    Date of Patent: December 11, 2012
    Assignee: Calos Fund Limited Liability Company
    Inventor: Peter Mattson
  • Patent number: 8327119
    Abstract: An apparatus executes a bit scan instruction that specifies an N-byte input operand. A first encoder forward bit scan encodes each input byte to generate N first bit vectors. A zero detector zero-detects each input byte to generate a second bit vector. A second encoder forward bit scan encodes the second bit vector to generate a third bit vector. An N:1 multiplexor, controlled by the third bit vector, selects one of the N first bit vectors to output a fourth bit vector. The apparatus concatenates the third and fourth bit vectors into a fifth bit vector that indicates the bit index of the least significant set bit of the input operand. A third encoder forward bit scan encodes a bit-reversed version of each input by to generate N sixth bit vectors. A fourth encoder forward bit scan encodes a bit-reversed version of the second bit vector to generate a seventh bit vector. A second N:1 multiplexor, controlled by the seventh bit vector, selects one of the N sixth bit vectors to output an eighth bit vector.
    Type: Grant
    Filed: October 21, 2009
    Date of Patent: December 4, 2012
    Assignee: VIA Technologies, Inc.
    Inventor: Bryan Wayne Pogor
  • Patent number: 8327116
    Abstract: An off-load for processing a data frame containing information has a memory for storing information on a plurality of processing paths. A processor in the off-load engine determines which processing path the data frame is to be processed. Each one of a plurality of processing engines processes the data frame depending on whether the processing engine is within the determined processing path. Some of the processing engines are implemented in hardware and/or data frame type specific software and others makes use of generic software. In some embodiments, the data frame is also parsed for further processing by the processing engines. In some embodiments, a static header is also pre-pended to the data frame to allow easy access to information associated with the data frame by the processing engines.
    Type: Grant
    Filed: December 8, 2003
    Date of Patent: December 4, 2012
    Assignee: Alcatel Lucent
    Inventors: Roger Maitland, Eric Combes
  • Patent number: 8316218
    Abstract: A wake-and-go mechanism is provided for a microprocessor. The wake-and-go mechanism looks ahead in the instruction stream of a thread for programming idioms that indicate that the thread is waiting for an event. if a look-ahead polling operation succeeds, the look-ahead wake-and-go engine may record an instruction address for the corresponding idiom so that the wake-and-go mechanism may have the thread perform speculative execution at a time when the thread is waiting for an event. During execution, when the wake-and-go mechanism recognizes a programming idiom, the wake-and-go mechanism may store the thread state in the thread state storage. Instead of putting the thread to sleep, the wake-and-go mechanism may perform speculative execution.
    Type: Grant
    Filed: February 1, 2008
    Date of Patent: November 20, 2012
    Assignee: International Business Machines Corporation
    Inventors: Ravi K. Arimilli, Satya P. Sharma, Randal C. Swanberg
  • Patent number: 8312187
    Abstract: An I/O device includes a host interface coupled to a plurality of hardware resources. The host interface includes a transaction layer packet (TLP) processing unit that may receive and process a plurality of transaction layer packets sent by a plurality of processing units. Each processing unit may correspond to a respective root complex. The TLP processing unit may identify a transaction type and a processing unit corresponding to each transaction layer packet and store each transaction layer packet within a storage according to the transaction type and the processing unit. The TLP processing unit may select one or more transaction layer packets from the storage for process scheduling based upon a set of fairness criteria using an arbitration scheme. The TLP processing unit may further select and dispatch transaction layer packets for processing by downstream application hardware based upon additional criteria.
    Type: Grant
    Filed: September 18, 2009
    Date of Patent: November 13, 2012
    Assignee: Oracle America, Inc.
    Inventors: Elisa Rodrigues, John E. Watkins
  • Patent number: 8302188
    Abstract: A tampering-prevention-process generation apparatus generates an output process instruction group to be executed by an execution processing apparatus in order to protect a first process instruction which causes the execution processing apparatus to assign a value to an assign-target variable. The tampering-prevention-process generation apparatus includes a branch-process-instruction-group generating unit configured to generate, as a part of the output process instruction group, a branch process instruction group which causes a processing route to branch to the first process instruction. The tampering-prevention-process generation apparatus also includes a dependent-process-instruction-group generating unit configured to generate, as a part of the output process instruction group, a dependent process instruction group which causes the execution processing apparatus to execute a process dependent on the value of the assign-target variable.
    Type: Grant
    Filed: July 18, 2007
    Date of Patent: October 30, 2012
    Assignee: Panasonic Corporation
    Inventors: Taichi Sato, Rieko Asai
  • Patent number: 8301811
    Abstract: A technique migrates data from a source array to a target array while preserving SCSI reservation compliance. The technique involves providing an active-to-passive instruction to the source array while a first SCSI reservation enables hosts to access data on the source array using MPIO software. The active-to-passive instruction directs the source array to transition devices from active mode to passive mode and, upon receipt of a next SCSI instruction, output an indicator indicating that the first SCSI reservation has been cleared. The technique further involves transitioning devices of the target array from passive mode to active mode and beginning a data transfer operation which transfers data from the source array to the target array. The technique further involves automatically effectuating formation of a second SCSI reservation in place of the first SCSI reservation, the second SCSI reservation providing host access to the data on the target array using MPIO software.
    Type: Grant
    Filed: March 30, 2010
    Date of Patent: October 30, 2012
    Assignee: EMC Corporation
    Inventors: Ian Wigmore, Patrick Brian Riordan, Michael Scharland, Arieh Don
  • Patent number: 8301870
    Abstract: A method and structure for an out-of-order processor executing at least two threads of instructions that communicate and synchronize with each other. The synchronization is achieved by monitoring addresses of instructions in at least one of the threads.
    Type: Grant
    Filed: July 27, 2006
    Date of Patent: October 30, 2012
    Assignee: International Business Machines Corporation
    Inventor: Krishnan Kunjunny Kailas
  • Patent number: 8301868
    Abstract: Method, apparatus, and system for monitoring performance within a processing resource, which may be used to modify user-level software. Some embodiments of the invention pertain to an architecture to allow a user to improve software running on a processing resources on a per-thread basis in real-time and without incurring significant processing overhead.
    Type: Grant
    Filed: September 23, 2005
    Date of Patent: October 30, 2012
    Assignee: Intel Corporation
    Inventors: Chris J. Newburn, Robert Knight, Robert Geva, Dion Rodgers, Xiang Zou, Hong Wang, Bryant E. Bigbee, Ittai Anati
  • Patent number: 8296551
    Abstract: A source computer system with one instruction set architecture (ISA) is configured to run on a target hardware system that has its own ISA, which may be the same as the source ISA. In cases where the source instructions cannot be executed directly on the target system, the invention provides binary translation system. During execution from binary translation, however, both synchronous and asynchronous exceptions may arise. Synchronous exceptions may be either transparent (requiring processing action wholly within the target computer system) or non-transparent (requiring processing that alters a visible state of the source system). Asynchronous exceptions may also be either transparent or non-transparent, in which case an action that alters a visible state of the computer system needs to be applied.
    Type: Grant
    Filed: March 5, 2009
    Date of Patent: October 23, 2012
    Assignee: VMware, Inc.
    Inventor: Edouard Bugnion
  • Patent number: 8296769
    Abstract: An order-relation analyzing apparatus collects assigned destination processor information, a synchronization process order and synchronization information, determines a corresponding element associated with a program among a plurality of elements indicating an ordinal value of the program based on the assigned destination processor information, when an execution of the program is started, and calculates the ordinal value indicated by the corresponding element for each segment based on the synchronization information, when the synchronization process occurs while executing the program. When a first corresponding element associated with a second program, of which the execution starts after the execution of a first program associated with the first corresponding element finishes, is determined, the ordinal value of the second program is calculated by calculating the ordinal value indicated by the first corresponding element.
    Type: Grant
    Filed: March 18, 2008
    Date of Patent: October 23, 2012
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hidenori Matsuzaki, Tatsuya Mori, Shigehiro Asano
  • Patent number: 8291197
    Abstract: A system and method for aggressive loop parallelization using speculative execution is disclosed. The method may include transforming code of a target application for concurrent execution, which may include adding an instruction to create a global address table entry for each store operation on which a load operation of a different loop iteration is dependent. The method may include replacing a standard load instruction with a special instruction configured to determine if an operand address of the load matches an operand address in one of the global address table entries. Another special instruction may remove a table entry following execution of the corresponding store operation. If an operand address of a load of a currently executing thread matches an operand address in the global address table, the method may include setting a checkpoint, completing execution of the thread in a pre-fetch mode, and re-executing the thread from the checkpoint.
    Type: Grant
    Filed: February 12, 2007
    Date of Patent: October 16, 2012
    Assignee: Oracle America, Inc.
    Inventors: Yuguang Wu, Jin Lin
  • Patent number: 8291202
    Abstract: Techniques for interrupt processing are described. An exceptional condition is detected in one or more stages of an instruction pipeline in a processor. In response to the detected exceptional condition and prior to the processor accepting an interrupt in response to the detected exceptional condition, an instruction cache is checked for the presence of an instruction at a starting address of an interrupt handler. The instruction at the starting address of the interrupt vector table is prefetched from storage above the instruction cache when the instruction is not present in the instruction cache to load the instruction in the instruction cache, whereby the instruction is made available in the instruction cache by the time the processor accepts the interrupt in response to the detected exceptional condition.
    Type: Grant
    Filed: August 8, 2008
    Date of Patent: October 16, 2012
    Inventors: Daren Eugene Streett, Brian Michael Stempel