Abstract: A method and apparatus for enabling usage of an accelerator device in a processor socket is herein described. A set of inter-processor messages is utilized to initialize a configuration/memory space of the accelerator device. As an example, a first set of inter-processor interrupts (IPIs) is sent to indicate a base address of a memory space and a second set of IPIs is sent to indicate a size of the memory space. Furthermore, similar methods and apparatus' are herein described for dynamic reconfiguration of an accelerator device in a processor socket.

Abstract: According to some embodiments, a technique provides for the execution of an instruction that includes receiving residual data of a first image and decoded pixels of a second image, zero-extending a plurality of unsigned data operands of the decoded pixels producing a plurality of unpacked data operands, adding a plurality of signed data operands of the residual data to the plurality of unpacked data operands producing a plurality of signed results; and saturating the plurality of signed results producing a plurality of unsigned results.

Abstract: The invention includes receiving a first instruction in an in-order execution processing pipeline; starting execution of the first instruction; determining a first set of internal operation bits indicating a prospective value of control bits upon complete execution of the first instruction; determining whether the first instruction is a committed instruction; receiving a second instruction in the in-order execution processing pipeline before execution of the first instruction completes; determining a second set of internal operation bits based on: a) the first set of internal operation bits if the first instruction is a committed instruction; or b) a set of internal operation bits of a last committed instruction if the first instruction is not a committed instruction; and starting execution of the second instruction in the in-order execution processing pipeline before execution of the first instruction completes using the second internal operation bits. Numerous other aspects are provided.

Abstract: Methods, apparatus, and products are disclosed for determining when a set of compute nodes participating in a barrier operation on a parallel computer are ready to exit the barrier operation that includes, for each compute node in the set: initializing a barrier counter with no counter underflow interrupt; configuring, upon entering the barrier operation, the barrier counter with a value in dependence upon a number of compute nodes in the set; broadcasting, by a DMA engine on the compute node to each of the other compute nodes upon entering the barrier operation, a barrier control packet; receiving, by the DMA engine from each of the other compute nodes, a barrier control packet; modifying, by the DMA engine, the value for the barrier counter in dependence upon each of the received barrier control packets; exiting the barrier operation if the value for the barrier counter matches the exit value.

Abstract: An integrated circuit includes a plurality of processor core. Processing instructions in the integrated circuit includes: managing a plurality of sets of processor cores, each set including one or more processor cores assigned to a function associated with executing instructions; and reconfiguring the number of processor cores assigned to at least one of the sets during execution based on characteristics associated with executing the instructions.

Abstract: A method and structure of distributing elements of an array of data in a computer memory to a specific processor of a multi-dimensional mesh of parallel processors includes designating a distribution of elements of at least a portion of the array to be executed by specific processors in the multi-dimensional mesh of parallel processors. The pattern of the designating includes a cyclical repetitive pattern of the parallel processor mesh, as modified to have a skew in at least one dimension so that both a row of data in the array and a column of data in the array map to respective contiguous groupings of the processors such that a dimension of the contiguous groupings is greater than one.

Abstract: An electronic circuit (4000) includes a bias value generator circuit (3900) operable to supply a varying bias value in a programmable range, and an instruction circuit (3625, 4010) responsive to a first instruction to program the range of said bias value generator circuit (3900) and further responsive to a second instruction having an operand to repeatedly issue said second instruction with said operand varied in an operand value range determined as a function of the varying bias value.

Abstract: A method and system for thread scheduling for optimal heat dissipation are provided. Temperature sensors measure temperature throughout various parts of a processor chip. The temperatures detected are reported to an operating system or the like for scheduling threads. In one aspect, the observed temperature values are recorded on registers. An operating system or the like reads the registers and schedules threads based on the temperature values.

Abstract: An integrated circuit includes a plurality of processor core. Processing instructions in the integrated circuit includes: managing a plurality of sets of processor cores, each set including one or more processor cores assigned to a function associated with executing instructions; and reconfiguring the number of processor cores assigned to at least one of the sets during execution based on characteristics associated with executing the instructions.

Abstract: An instruction processing circuit includes a decoder circuit operable to receive a sequence of instructions and to decode the received sequence of instructions into a first type of sequence of operations, and a trace builder circuit operable to receive at least a portion of the sequence of operations of the first type and to generate, based thereon, a second type of sequence of operations, where the at least a portion of the sequence of operations of the first type represents a first portion of the sequence of instructions, where the first portion of the sequence of instructions includes at most one conditional control transfer instruction that, when present, ends the first portion of the sequence of instructions, and where the sequence of operations of the second type also represents the first portion of the sequence of instructions.

Abstract: Certain embodiments for reducing instruction storage space for a processor integrated in a network adapter chip may include generating MIPS instructions from corresponding new instructions. The new instructions may be in patch code instruction (PCI) format. The new instructions may be decoded and the MIPS instructions may be generated by a MIPS processor within a network adapter chip. Decoding the new instructions may also be referred to as interpreting the new instructions. The new instructions may comprise fewer bits than the generated MIPS instructions. The generated MIPS instructions may be executed by the MIPS processor within the network adapter chip.

Abstract: The present invention provides a system and method for managing load and store operations necessary for reading from and writing to memory or I/O in a superscalar RISC architecture environment. To perform this task, a load store unit is provided whose main purpose is to make load requests out of order whenever possible to get the load data back for use by an instruction execution unit as quickly as possible. A load operation can only be performed out of order if there are no address collisions and no write pendings. An address collision occurs when a read is requested at a memory location where an older instruction will be writing. Write pending refers to the case where an older instruction requests a store operation, but the store address has not yet been calculated. The data cache unit returns 8 bytes of unaligned data. The load/store unit aligns this data properly before it is returned to the instruction execution unit.

Abstract: Provided are a central processing unit (CPU) and method for executing a branch instruction of a CPU, which can protect user's data by preventing an error due to a computer virus and a hacker is provided. The CPU includes: a branch instruction verification unit which verifies whether a branch instruction is valid; and a branch instruction execution unit which executes the branch instruction when the branch instruction is valid. The method includes: verifying whether the branch instruction is valid; and not executing the branch instruction when the branch instruction is invalid.

Abstract: Disclosed are a method and system of tracking real time use of I/O control blocks on a processing unit basis, in a multiprocessing system, such that in the case of a processing unit failure, a list accurately and concisely identifies the control blocks that need to be recovered. This eliminates the need to scan all the I/O control blocks, greatly reducing the overall system recovery time and minimizing impact to the rest of the running system. The preferred embodiment of the invention uses a task control block structure to record which I/O control blocks are in use by each Processing Unit. Also, the lock word structure defined in the I/O control blocks is provided with an index back into the task control block to facilitate managing the task control block entries.

Abstract: Processor resource management devices and methods are disclosed. In some implementations, a device includes a processor, a hardware resource, and a resource manager operable to compare a first execution of one or more instructions pursuant to an optimistic resource management policy and a second execution of one or more instructions pursuant to a pessimistic resource management policy, the optimistic resource management policy assuming that less than an optimistic level of at least one error will occur during the first execution, and the pessimistic resource management policy assuming that greater than a pessimistic level of the at least one error will occur during the second execution. Based at least partially on the comparison, the resource manager selects a resource management policy from between the optimistic and pessimistic resource management policies, and associates the selected resource management policy with the one or more instructions.

Abstract: A system to prevent livelock. An outcome of an event is predicted to form an event outcome prediction. The event outcome prediction is compared with a correct value for a datum to be accessed. An instruction is appended with a real event outcome when the outcome of the event is mispredicted to form an appended instruction. A prediction override bit is set on the appended instruction. Then, the appended instruction is executed with the real event outcome.

Abstract: A multiplexed hierarchical array of interrupt controllers is configured to enable low latency task switching of a processor. The hierarchical array comprises a plurality of interrupt controllers coupled to a root interrupt controller. For each task that the processor is configured to execute, a corresponding interrupt controller is provided. To switch the processor to a task, the corresponding interrupt controller signals the root interrupt controller which, in turn, sends an interrupt and a Task Identifier to the processor. The root interrupt controller also cooperates with an access multiplexer/demultiplexer to select the corresponding interrupt controller for communication with the processor. By providing interrupt controller selection as well as task identification, the hierarchical array offloads arbitration and context switching overhead from the processor. That is, in response to the interrupt, the processor switches to the identified task and may access a memory address space dedicated to the task.

Abstract: Whenever a link address is written to the link stack, the prior value of the link stack entry is saved, and is restored to the link stack after a link stack push operation is speculatively executed following a mispredicted branch. This condition is detected by maintaining a count of the total number of uncommitted link stack write instructions in the pipeline, and a count of the number of uncommitted link stack write instructions ahead of each branch instruction. When a branch is evaluated and determined to have been mispredicted, the count associated with it is compared to the total count. A discrepancy indicates a link stack write instruction was speculatively issued into the pipeline after the mispredicted branch instruction, and pushed a link address onto the link stack. The prior link address is restored to the link stack from the link stack restore buffer.

Abstract: A process, apparatus, and system to execute a program in an array of processor nodes that include an agent node and an executor node. A virtual program of tokens of different types represents the program and is provided in a memory. The types include a run type that includes native code instructions of the executer node. A token is loaded from the memory and executed in the agent node based on its type. In particular, if the token is an optional stop type execution ends and if the token is a run type the native code instructions in the token are sent to the executor node. The native code instructions are executed in the executor node as received from the agent node. And such loading and execution continues in this manner indefinitely or until a stop type token is executed.

Abstract: A system for conditional memory ordering implemented in a multiprocessor environment. A conditional memory ordering instruction executes locally using a release vector containing release numbers for each processor in the system. The instruction first determines whether a processor identifier of the release number is associated with the current processor. Where it is not, a conditional registered is examined and appropriate remote synchronization operations are commanded where necessary.