Patents Examined by Edward J. Wojciechowicz
  • Patent number: 5247349
    Abstract: Pnictide thin films, particularly phosphorus, grown on III-V semiconductors, particularly InP, GaP, and GaAs, are amorphous and have a novel layer-like, puckered sheet-like local order. The thin films are typically 400 Angstroms thick and grown preferably by molecular beam deposition, although other processes such as vacuum evaporation, sputtering, chemical vapor deposition, and deposition from a liquid melt may be used. The layers are grown on the <100> <110>, and surfaces of the III-V crystals. The pnictide layer reduces the density of surface states, and allows the depletion layer to be modulated, the surface barrier reduced, the electron concentration at the surface increased, and there is a decrease in the surface recombination velocity and an increase in the photoluminescence intensity.
    Type: Grant
    Filed: August 22, 1990
    Date of Patent: September 21, 1993
    Assignee: Stauffer Chemical Company
    Inventors: Diego J. Olego, John A. Baumann, Rozalie Schachter, Harvey B. Serreze, William E. Spicer, Paul M. Raccah
  • Patent number: 5231299
    Abstract: An electrically programmable and electrically erasable memory cell (EEPROM) formed in a silicon body is described. The cell includes a silicon body or substrate with shallow trench isolation regions disposed therein. First and second spaced-apart source and drain regions of a first conductivity type are provided with a channel region in between. A first gate member, a floating gate, which is completely surrounded by insulation extends from at least the edge of the source region, over the channel region to at least the edge of the drain region. A second gate member, a control gate, includes a portion which extends over the floating gate. The control gate extends from at least the edge of the source region, over the channel region to at least the edge of the drain region. The channel region beneath the floating gate has both a highly doped portion and a lightly doped portion.
    Type: Grant
    Filed: March 24, 1992
    Date of Patent: July 27, 1993
    Assignee: International Business Machines Corporation
    Inventors: Tak H. Ning, Ching-Hsiang Hsu
  • Patent number: 5214308
    Abstract: A substrate for packaging a semiconductor device having a bump thereon according to the present invention is characterized by that the substrate has an electrode terminal to which the bump is to be connected, and a recess for receiving at least a top of the bump is formed in the electrode terminal.
    Type: Grant
    Filed: January 23, 1991
    Date of Patent: May 25, 1993
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Masanori Nishiguchi, Atsushi Miki
  • Patent number: 5212542
    Abstract: A complementary field effect transistor with an N channel MOSFET and a P channel MOSFET formed on the same substrate is disclosed. On the P type main surface of the semiconductor substrate, an N channel MOSFET is formed comprising a gate electrode and a pair of impurity regions which becomes a pair of source/drain regions. Each impurity region of the N channel MOSFET comprises an impurity region of relatively low concentration formed so as to extend to beneath the above mentioned gate electrode, and an impurity region having a concentration higher than that of said impurity region having low concentration formed in a position at a distance from said gate electrode joining the impurity region of low concentration. The length of the portion located beneath the above mentioned gate electrode in the surface portion of the impurity region of low concentration is not less than 0.1 .mu.m in the direction identical to the direction of the channel length.
    Type: Grant
    Filed: March 26, 1991
    Date of Patent: May 18, 1993
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventor: Yoshinori Okumura
  • Patent number: 5212400
    Abstract: A method of depositing tungsten on a substrate utilizing silicon reduction wherein the process is non-limiting as to the thickness of silicon that may be converted to tungsten. A silicon substrate is provided with at least one area of silicon material having a predetermined thickness and the substrate is exposed to a tungsten hexafluoride gas flow in a chemical vapor deposition environment. By adjusting the WF.sub.6 gas flow rate and the CVD process parameters, such as pressure, temperature and deposition time, the thickness of silicon converted to tungsten can be adjusted in order to convert the entire thickness. A novel structure having a midgap tungsten gate and tungsten source and drain metallized layers is also disclosed.
    Type: Grant
    Filed: September 3, 1991
    Date of Patent: May 18, 1993
    Assignee: International Business Machines Corporation
    Inventor: Rajiv V. Joshi
  • Patent number: 5208469
    Abstract: A wafer scale integrated circuit includes a plurality of functional circuit blocks arranged in rows on a wafer, each functional circuit block having four corners, and a signal propagation path (spiral) serially connecting some of the plurality of functional circuit blocks. Each functional circuit block is arranged in a zigzag manner such that at least two corners of a functional circuit block in one row are located approximately in the center of respective sides of corresponding functional circuit block in a row adjacent to that row. As a result, it is possible to reduce the number of branch signal paths to the lowest possible value when forming the spiral, and thus facilitate an external control for forming the spiral to thereby shorten a processing time needed for the control, while increasing a utilization efficiency of non-defective chips.
    Type: Grant
    Filed: July 5, 1991
    Date of Patent: May 4, 1993
    Assignee: Fujitsu Limited
    Inventor: Toshiyuki Hodoshima
  • Patent number: 5206534
    Abstract: In the case of a photocell based on gallium arsenide or indium phosphide, a layer of amorphous, hydrogenous carbon (a-C:H) having a thickness of .ltoreq.0.1 .mu.m and a specific electrical resistance of .gtoreq.10.sup.6 .OMEGA..cm is placed on a layer of p-doped gallium arsenide (GaAs) or indium phosphide (InP).
    Type: Grant
    Filed: August 20, 1991
    Date of Patent: April 27, 1993
    Assignee: Siemens Aktiengesellschaft
    Inventors: Siegfried Birkle, Johann Kammermaier, Gerhard Rittmayer
  • Patent number: 5206535
    Abstract: A semiconductor device composed of a substrate provided with a groove filled with insulating material to define an element isolating region. The groove corners are rounded and the substrate contains impurity material below the groove and in a region adjacent the groove. The impurity material is introduced to have essentially the same impurity density profile below the bottom of the groove and below the substrate surface in the region adjacent the groove.The device may additionally be provided, if the region below and adjacent the groove is of P-type conductivity, with a buried P-type layer which opposes penetration of .alpha. particle radiation into the substrate.
    Type: Grant
    Filed: May 1, 1990
    Date of Patent: April 27, 1993
    Assignee: Seiko Epson Corporation
    Inventor: Isamu Namose
  • Patent number: 5206536
    Abstract: A comb insert for semiconductor packaged devices is disclosed. The comb is conductive and thus useful to function as a power supply bus in transferring power to the semiconductor die. A base, formed out of a conductive material, resides underneath the lead fingers of the semiconductor packaged device, electrically isolated from the lead fingers. The base has teeth extending from it, also formed out of the conductive material, that reside between the lead fingers of the semiconductor packaged device. Some of the teeth are electrically connected to the lead fingers for receiving external power. Some of the teeth are electrically connected to the bonding pads of the semiconductor die. Power is transferred from the lead fingers for receiving it, through the teeth electrically connected to these lead fingers, through the base, through the teeth electrically connected to the bonding pads, and to the semiconductor die.
    Type: Grant
    Filed: January 23, 1991
    Date of Patent: April 27, 1993
    Assignee: Texas Instruments, Incorporated
    Inventor: Thiam B. Lim
  • Patent number: 5196918
    Abstract: An integrated circuit device having an electronic circuit component connected by wire-bonding is characterized in that a masking member having a lower sputtering rate than that of the material forming the electrodes to be used for the wire-bonding is arranged around the electronic circuit component. A method for manufacturing an integrated circuit device having an electronic circuit component connected by wire-bonding is characterized in that a masking member having a lower sputtering rate than that of the material forming the electrodes to be used for the wire-bonding is arranged around the electronic circuit component.
    Type: Grant
    Filed: November 18, 1991
    Date of Patent: March 23, 1993
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Mitsuaki Fujihira, Yoshiaki Tanaka
  • Patent number: 5196718
    Abstract: A high efficiency, high density light-emitting diode array which provides improved light output efficiency and suppression of crosstalk between adjacent light-emitting elements without loss of reliability or reproducibility is disclosed. The array includes isolated light-emitting elements on a substrate. Each light-emitting element has a light-emitting layer between a pair of cladding layers with heterojunctions being formed between the light-emitting layer and the cladding layers. Each light-emitting element has a light-emitting surface and the light-emitting layer of each light-emitting element is of an area no greater than the area of the light-emitting surface.
    Type: Grant
    Filed: August 13, 1991
    Date of Patent: March 23, 1993
    Assignee: Eastman Kodak Company
    Inventor: Teruo Sasagawa
  • Patent number: 5192992
    Abstract: A BICMOS device and manufacturing method wherein the gates of PMOS and NMOS transistors are formed by forming a first polysilicon layer which is not implanted by an impurity and forming a second polysilicon layer on the first polysilicon layer which is impurity implanted, so that the impurity doped in the second polysilicon layer is prevented from diffusing into the channel region and the voltage characteristic is prevented from changing. Emitter regions of vertical PNP and NPN bipolar transistors are self-aligned in a small chip area, and thereby the performance of the BICMOS device is improved due to the stable threshold voltage characteristic of the PMOS and NMOS transistors and high density is achieved together with improved operation speed clue to the self-alignment formation of the emitter region of the vertical PNP and NPN bipolar transistors.
    Type: Grant
    Filed: November 18, 1991
    Date of Patent: March 9, 1993
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Myung S. Kim, Jong G. Kim, Hyun S. Kim
  • Patent number: 5189502
    Abstract: A semiconductor device including a first wiring layer, and insulator layer formed on the first wiring layer and including a first silicon oxide film, a spin-coated insulating film formed on the first silicon oxide film and a second silicon oxide film formed on the spin-coated insulating film, a through-hole selectively formed in the insulator layer to expose a part of the first wiring layer, and a second wiring layer formed on the insulator layer and in contact with the part of the first wiring layer exposed through the through-hole, wherein the second silicon oxide film has a density lower than the density of the first silicon oxide film and allows gas from the spin-coated insulating film to go through the second silicon oxide film.
    Type: Grant
    Filed: May 7, 1991
    Date of Patent: February 23, 1993
    Assignee: NEC Corporation
    Inventor: Hideki Gomi
  • Patent number: 5189506
    Abstract: A process is described which eliminates the need to account for mask alignment tolerances in forming vias for metallurgy by the use of a common vertical edge or common plane defined by a first mask representing a first level of interconnect. Subsequent masks for defining interconnecting vias and a second level of interconnect utilize at least one edge of the first mask pattern as a common element to define subsequent metal levels. The combination of an etch stop layer and an oversized second level mask enable the mask overlay to be eliminated.
    Type: Grant
    Filed: June 3, 1992
    Date of Patent: February 23, 1993
    Assignee: International Business Machines Corporation
    Inventors: John E. Cronin, Carter W. Kaanta
  • Patent number: 5187379
    Abstract: A field effect transistor includes a semi-insulating substrate, first conductivity type source and drain regions disposed in the substrate, a first conductivity type channel layer having a lower dopant concentration than the source and drain regions and disposed between and connecting the source and drain regions, and a second conductivity type buried region disposed in the substrate adjacent to and contacting the first conductivity type channel layer but not contacting the source and drain regions. The leakage current from the channel region is greatly reduced without increasing the parasitic gate capacitance.
    Type: Grant
    Filed: September 13, 1991
    Date of Patent: February 16, 1993
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventor: Minoru Noda
  • Patent number: 5187556
    Abstract: A CMOS master slice having a plurality of regularly arranged basic cells improves an integration efficiency by optimizing size and arrangement of MOS transistors in the basic cells. Each of the basic cells comprises a first pair of transistors having gates thereof arranged to parallelly face each other, and a second pair of transistors having gate electrodes shorter in gate width than that of the first pair of transistors and parallel to the gate electrodes of the first pair of transistors. In adjacent basic cells, the gate electrodes of adjacent second transistors are substantially on a line so that a wasteful space is eliminated.
    Type: Grant
    Filed: August 9, 1991
    Date of Patent: February 16, 1993
    Assignee: Kawasaki Steel Corporation
    Inventors: Masaaki Nariishi, Noboru Yamakawa, Osamu Ohba, Naoyasu Seki
  • Patent number: 5185535
    Abstract: Complimentary metal oxide silicon transistors fabricated on silicon-on-insulator substrates are configured to allow separately controllable and independent backgate bias for adjacent complimentary devices on the same substrate. By means of deep implantation of boron, a backgate bias P- well (26,126) is positioned on the N-substrate (17,117) at a front surface of the N- substrate behind the N channel transistor of a complimentary pair. The backgate bias P- well (26,126) is provided with an electrical contact (48,148) at the front of the device, as is the N- silicon substrate to enable independent application of separate bias voltage of different polarities and appropriate magnitude.
    Type: Grant
    Filed: June 17, 1991
    Date of Patent: February 9, 1993
    Assignee: Hughes Aircraft Company
    Inventors: Joseph E. Farb, Mei Li, Chen-Chi P. Chang, Maw-Rong Chin
  • Patent number: 5178370
    Abstract: A vertical conducting insulating gate bipolar transistor having an emitter region formed in a base region wherein the base region is not shorted to the emitter is provided. The emitter and base regions are formed in an upper portion of a lightly doped semiconductor drift region and an anode region is formed in a bottom portion of the drift region. During forward conduction, minority carriers are injected from the anode into the base region, biasing the base region sufficiently to inject minority carriers into the upper surface of the drift region. The injected minority carriers improve conductivity in the upper portion of the drift region.
    Type: Grant
    Filed: August 5, 1991
    Date of Patent: January 12, 1993
    Assignee: Motorola Inc.
    Inventors: Lowell E. Clark, Robert B. Davies
  • Patent number: 5175603
    Abstract: A bipolar transistor excellent in the high speed performance comprises a buried region of a first conductivity type formed in a semiconductor substrate, said buried region having a high impurity concentration, a collector region of the first conductivity type formed on the buried region, a base region of a second conductivity type formed on the collector region, an emitter region of the first conductivity type formed on the base region, and an outer base region of the second conductivity type formed to surround the base and collector regions in such a manner that an ohmic contact is provided between the base region and said outer base region and a p-n junction is formed between the collector region and said outer base region.
    Type: Grant
    Filed: December 10, 1991
    Date of Patent: December 29, 1992
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Toshihiko Hamasaki
  • Patent number: RE34158
    Abstract: A monolithic complementary semiconductor device comprising n-type and p-type well regions separated by a dielectric isolation region extending from the surface into the substrate region. The well region includes a highly doped buried region which is located at the bottom of the well region and separates an active region in the wall from the substrate region. The isolation region is deeper than the buried region. The well-to-well isolation is enhanced by the combination of the buried region and the deep dielectric isolation region. Packing density and the high speed operation can also be improved.
    Type: Grant
    Filed: August 13, 1991
    Date of Patent: January 12, 1993
    Assignee: Hitachi, Ltd.
    Inventors: Atsuo Watanabe, Takahiro Nagano, Takahide Ikeda, Naohiro Momma, Ryuichi Saito